公开(公告)号：US08389414B2

公开(公告)日：2013-03-05

申请号：US13026651

申请日：2011-02-14

Applicant: Katsumi Kikuchi ,  Shintaro Yamamichi ,  Hideya Murai ,  Takuo Funaya ,  Kentaro Mori ,  Takehiko Maeda ,  Hirokazu Honda ,  Kenta Ogawa ,  Jun Tsukano

Inventor： Katsumi Kikuchi ,  Shintaro Yamamichi ,  Hideya Murai ,  Takuo Funaya ,  Kentaro Mori ,  Takehiko Maeda ,  Hirokazu Honda ,  Kenta Ogawa ,  Jun Tsukano

IPC: H01L21/311

CPC classification number: H05K3/205 ,  H01L21/4857 ,  H01L21/486 ,  H01L21/563 ,  H01L23/498 ,  H01L23/49822 ,  H01L23/49827 ,  H01L24/45 ,  H01L24/48 ,  H01L24/73 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48228 ,  H01L2224/48472 ,  H01L2224/73203 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2224/92247 ,  H01L2924/00014 ,  H01L2924/01019 ,  H01L2924/01046 ,  H01L2924/01057 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01322 ,  H01L2924/09701 ,  H01L2924/12044 ,  H01L2924/181 ,  H01L2924/19041 ,  H05K3/244 ,  H05K3/423 ,  H05K2201/0338 ,  H05K2201/098 ,  H05K2201/09845 ,  H05K2203/0376 ,  H05K2203/0384 ,  H05K2203/0733 ,  H05K2203/1476 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/05599 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A wiring board has an insulating layer, a plurality of wiring layers formed in such a way as to be insulated from each other by the insulating layer, and a plurality of vias formed in the insulating layer to connect the wiring layers. Of the wiring layers, a surface wiring layer formed in one surface of the insulating layer include a first metal film exposed from the one surface and a second metal film embedded in the insulating layer and stacked on the first metal film. Edges of the first metal film project from edges of the second metal film in the direction in which the second metal film spreads. By designing the shape of the wiring layers embedded in the insulating layer in this manner, it is possible to obtain a highly reliable wiring board that can be effectively prevented from side etching in the manufacturing process and can adapt to miniaturization and highly dense packaging of wires.

Abstract translation: 布线基板具有绝缘层，多个布线层以通过绝缘层彼此绝缘的方式形成，以及形成在绝缘层中以连接布线层的多个通孔。 在布线层中，形成在绝缘层的一个表面上的表面布线层包括从一个表面露出的第一金属膜和嵌入在绝缘层中并叠放在第一金属膜上的第二金属膜。 第一金属膜的边缘沿着第二金属膜扩展的方向从第二金属膜的边缘突出。 通过以这种方式设计嵌入在绝缘层中的布线层的形状，可以获得在制造过程中可以有效地防止侧蚀刻的高可靠性布线板，并且可以适应电线的小型化和高密度封装 。

公开(公告)号：US20130049202A1

公开(公告)日：2013-02-28

申请号：US13331253

申请日：2011-12-20

Applicant: Makoto TANI ,  Takami Hirai ,  Shinsuke Yano ,  Daishi Tanabe

Inventor： Makoto TANI ,  Takami Hirai ,  Shinsuke Yano ,  Daishi Tanabe

IPC: H01L23/48 ,  H05K1/09 ,  H05K1/00

CPC classification number: H05K3/4629 ,  H01L23/49822 ,  H01L23/49838 ,  H01L23/5283 ,  H01L2924/0002 ,  H05K1/0242 ,  H05K3/4623 ,  H05K2201/09227 ,  H05K2201/09236 ,  H05K2201/098 ,  H05K2201/09827 ,  H01L2924/00

Abstract: In the laminated and sintered ceramic circuit board according to the present invention, at least a portion of the inplane conductor is fine-lined, such that the shape of the cross-section surface of the fine-lined inplane conductor is trapezoid, and the height (a), the length (c) of the lower base and the length (d) of the upper base of the trapezoidal cross-section surfaces, and the interval (b) between the lower bases of the trapezoidal cross-section surfaces of the inplane conductors adjacent in a plane parallel to the principal surfaces of the board meet a certain relation. This provides a laminated ceramic circuit hoard with low open failure rate, short-circuit failure rate and high reliability against high temperature and high humidity in a downsized and short-in-height (thin) semiconductor package.

Abstract translation: 在根据本发明的层压和烧结陶瓷电路板中，面内导体的至少一部分被精细地排列，使得细衬面内导体的横截面的形状是梯形，并且高度 （a）中，梯形截面的下基部的长度（c）和上基部的长度（d）以及梯形截面的梯形截面的下基座之间的间隔（b） 在与板的主表面平行的平面中相邻的面内导体满足一定关系。 这提供了在小型和短路（薄）半导体封装中具有低开路故障率，短路故障率和高温和高湿度的高可靠性的层压陶瓷电路板。

公开(公告)号：US08338712B2

公开(公告)日：2012-12-25

申请号：US12969478

申请日：2010-12-15

Applicant: Vinh T. Nguyen ,  Claude A. S. Hamrick

Inventor： Vinh T. Nguyen ,  Claude A. S. Hamrick

IPC: H05K1/00

CPC classification number: H05K3/1258 ,  H05K3/108 ,  H05K3/125 ,  H05K3/243 ,  H05K3/4611 ,  H05K3/4623 ,  H05K2201/09318 ,  H05K2201/09327 ,  H05K2201/09536 ,  H05K2201/098 ,  H05K2203/013 ,  H05K2203/0568 ,  Y10T29/49002 ,  Y10T29/49124 ,  Y10T29/49126 ,  Y10T29/49144 ,  Y10T29/49155 ,  Y10T29/49165

Abstract: A multilayer circuit device having electrically isolated tightly spaced electrical current carrying traces and including a first nonconductive substrate having a first conductive material affixed to a first side thereof to form a first ground plane, a plurality of elongated first conductive traces formed on a second side of the first non-conductive substrate and having transverse widths of 50 microns or less and rising above the upper surface of the first substrate to a height equal to or greater than the widths thereof such that a transverse cross section of the first conductive traces has a height-to-width ratio equal to or exceeding 1, adjacent ones of the first traces being separated from each other by first elongated spaces, the first conductive traces being variously useful as ground lines, signal lines and/or power lines.

Abstract translation: 一种具有电隔离紧密间隔的电流载流迹线并包括第一非导电基底的多层电路器件，所述第一非导电基底具有固定到其第一侧的第一导电材料以形成第一接地平面;多个细长的第一导电迹线，形成在第二侧 第一非导电衬底并且具有50微米或更小的横向宽度并且在第一衬底的上表面上方升高到等于或大于其宽度的高度，使得第一导电迹线的横截面具有高度 宽度比等于或超过1，相邻的第一迹线通过第一细长空间彼此分开，第一导电迹线在各种不同地用作接地线，信号线和/或电力线。

公开(公告)号：US08304659B2

公开(公告)日：2012-11-06

申请号：US11977783

申请日：2007-10-26

Applicant: Joel R. Goergen

Inventor： Joel R. Goergen

IPC: H05K1/00

CPC classification number: H05K1/0242 ,  H01P3/081 ,  H05K1/0245 ,  H05K2201/09236 ,  H05K2201/09745 ,  H05K2201/098 ,  Y10T29/49126

Abstract: Circuit boards and methods for their manufacture are disclosed. The circuit boards carry high-speed signals using conductors formed to include lengthwise channels. The channels increase the surface area of the conductors, and therefore enhance the ability of the conductors to carry high-speed signals. In at least some embodiments, a discontinuity also exists between the dielectric constant within the channels and just outside the channels, which is believed to reduce signal loss into the dielectric material.

Abstract translation: 公开了电路板及其制造方法。 电路板使用形成为包括纵向通道的导体承载高速信号。 通道增加了导体的表面积，从而增强了导体承载高速信号的能力。 在至少一些实施例中，通道内的介电常数和通道之外的介质常数之间也存在不连续性，这被认为可减少信号损耗。

公开(公告)号：US20120270158A1

公开(公告)日：2012-10-25

申请号：US13541664

申请日：2012-07-04

Applicant: CHIH-KUANG YANG

Inventor： CHIH-KUANG YANG

IPC: G03F7/20

CPC classification number: H05K3/4007 ,  H05K1/111 ,  H05K1/118 ,  H05K3/048 ,  H05K2201/0367 ,  H05K2201/098 ,  H05K2201/09845 ,  H05K2201/099 ,  H05K2203/0588 ,  H05K2203/0594 ,  Y10T29/4913 ,  Y10T29/49165

Abstract: Disclosed is a metal structure of a multi-layer substrate, comprising a first metal layer and a dielectric layer. The first metal layer has an embedded base and a main body positioned on the embedded base. The base area of the embedded base is larger than the base area of the main body. After the dielectric layer covers the main body and the embedded base, the dielectric layer is opened at the specific position of the first metal layer for connecting the first metal layer with a second metal layer above the dielectric layer. When the metal structure is employed as a pad or a metal line of the flexible multi-layer substrate according to the present invention, the metal structure cannot easily be delaminated or separated from the contacted dielectric layer. Therefore, a higher reliability for the flexible multi-layer substrate can be achieved. A manufacturing method thereof is also provided.

Abstract translation: 公开了包括第一金属层和电介质层的多层基板的金属结构。 第一金属层具有嵌入式基座和位于嵌入式基座上的主体。 嵌入式基座的基座面积大于主体的基座面积。 在电介质层覆盖主体和嵌入式基底之后，电介质层在第一金属层的特定位置处开口，用于将第一金属层与电介质层上方的第二金属层连接。 当金属结构用作根据本发明的柔性多层基板的焊盘或金属线时，金属结构不容易从接触的介电层分层或分离。 因此，可以实现柔性多层基板的更高的可靠性。 还提供了其制造方法。

公开(公告)号：US08222531B2

公开(公告)日：2012-07-17

申请号：US12840792

申请日：2010-07-21

Applicant: Tomofumi Kitada ,  Hiroki Maruo ,  Ryo Takami

Inventor： Tomofumi Kitada ,  Hiroki Maruo ,  Ryo Takami

IPC: H05K1/03

CPC classification number: H05K3/363 ,  H01L2924/0002 ,  H05K2201/09745 ,  H05K2201/098 ,  H05K2201/09845 ,  H01L2924/00

Abstract: A board interconnection structure having a first printed wiring board in which a first conductive circuit is arranged on a first insulating layer, the first conductive circuit having, on an end portion thereof, a first connection terminal in which an upper surface width is narrower than a bottom surface width; a second printed wiring board in which a second conductive layer having a second connection terminal is arranged on a second insulating layer; and a connection layer that forms fillets along longitudinal side surfaces of the first connection terminal, and interconnects the first connection terminal and the second connection terminal. The first connection terminal may have a projection portion.

Abstract translation: 一种电路板互连结构，具有第一印刷线路板，其中第一导电电路布置在第一绝缘层上，所述第一导电电路在其端部上具有第一连接端子，其中上表面宽度窄于 底面宽度; 第二印刷线路板，其中具有第二连接端子的第二导电层布置在第二绝缘层上; 以及连接层，其沿着所述第一连接端子的纵向侧表面形成圆角，并且将所述第一连接端子和所述第二连接端子互连。 第一连接端子可以具有突出部分。

公开(公告)号：US08198544B2

公开(公告)日：2012-06-12

申请号：US12821196

申请日：2010-06-23

Applicant: Toru Nakai ,  Masanori Tamaki

Inventor： Toru Nakai ,  Masanori Tamaki

IPC: H05K1/03

CPC classification number: H05K1/0242 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/16225 ,  H01L2924/15311 ,  H05K1/0216 ,  H05K1/0245 ,  H05K3/28 ,  H05K3/4602 ,  H05K3/4644 ,  H05K2201/09236 ,  H05K2201/098

Abstract: A printed wiring board including resin insulation layers, and conductive circuits formed between the resin insulation layers such that spaces between the conductive circuits are filled with a resin material of the resin insulation layers. The conductor circuits include a first conductive circuit and a second conductive circuit positioned adjacent to the first conductive circuit, each of the first and second conductive circuits has a trapezoidal cross section, and the first and the second conductive circuits satisfy a formula, 0.10T≦|W1−W2|≦0.73T where W1 represents a width of a space between upper surfaces of the first and second conductive circuits, W2 represents a width of a space between lower surfaces of the first and second conductive circuits, and T represents a thickness of each of the first and second conductive circuit.

Abstract translation: 一种包括树脂绝缘层的印刷线路板和形成在树脂绝缘层之间的导电电路，使得导电电路之间的空间被树脂绝缘层的树脂材料填充。 所述导体电路包括第一导电电路和邻近所述第一导电电路定位的第二导电电路，所述第一和第二导电电路中的每一个具有梯形横截面，并且所述第一和第二导电电路满足公式：0.10T＆nlE; | W1-W2 |＆nlE; 0.73T其中W1表示第一和第二导电电路的上表面之间的间隔的宽度，W2表示第一和第二导电电路的下表面之间的空间的宽度，T表示 每个第一和第二导电电路的厚度。

公开(公告)号：US08102234B2

公开(公告)日：2012-01-24

申请号：US12691950

申请日：2010-01-22

Applicant: Shuichi Ozawa ,  Natsumi Shimogawa ,  Katsuyuki Takeuchi ,  Yukio Aisaka

Inventor： Shuichi Ozawa ,  Natsumi Shimogawa ,  Katsuyuki Takeuchi ,  Yukio Aisaka

IPC: H01F5/00

CPC classification number: H01F17/0013 ,  H01F41/046 ,  H01F2017/002 ,  H01F2017/0066 ,  H05K1/165 ,  H05K3/4629 ,  H05K2201/083 ,  H05K2201/09672 ,  H05K2201/098

Abstract: A layered inductor is manufactured by layering “silver-based conductive layers” and “ferrite-based magnetic layers” and simultaneously firing these layers. The conductive layers are via-connected to form a helical coil. A shape of a cross sectional surface of the conductive layer, cut by a plane perpendicular to a longitudinal direction of each of the conductive layers is a substantial trapezoid shape, having an upper base and a lower base. A base angle θ of the trapezoid shape at both ends of the lower base is equal to or greater than 50° and is smaller than or equal to 80°.

Abstract translation: 通过层叠“银基导电层”和“铁氧体基磁性层”并同时烧制这些层来制造层状电感器。 导电层通孔连接形成螺旋线圈。 由垂直于每个导电层的纵向的平面切割的导电层的横截面的形状是具有上基部和下基部的实质梯形形状。 底角角度; 在下底座两端的梯形形状等于或大于50°并且小于或等于80°。

公开(公告)号：US08016184B2

公开(公告)日：2011-09-13

申请号：US12887542

申请日：2010-09-22

Applicant: Koichi Kanryo ,  Akio Katsube ,  Akira Tanaka

Inventor： Koichi Kanryo ,  Akio Katsube ,  Akira Tanaka

IPC: B23K31/02 ,  B05D5/12

CPC classification number: H05K1/0218 ,  H01L23/552 ,  H01L24/97 ,  H01L25/165 ,  H01L25/50 ,  H01L2224/16225 ,  H01L2224/97 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/09701 ,  H01L2924/12041 ,  H01L2924/15159 ,  H01L2924/19105 ,  H05K3/0052 ,  H05K3/284 ,  H05K2201/098 ,  H05K2203/1316 ,  H01L2224/81

Abstract: A method for manufacturing an electronic component module is performed such that a shield layer can be formed as a thin film and an electronic component can be effectively shielded. A collective substrate including a plurality of electronic component modules including a plurality of electronic components is batch-sealed with a resin. A cut section is formed from a top surface of the sealed resin to a position that reaches a grounding electrode arranged in the substrate at a boundary section of the electronic component module so as to expose the grounding electrode. A conductive paste is applied on side surfaces and the top surface. Then, a conductive thin film is formed by spin coating, and the electronic component module is cut.

Abstract translation: 执行电子部件模块的制造方法，使得可以形成屏蔽层作为薄膜，并且可以有效地屏蔽电子部件。 包括多个电子部件的多个电子部件模块的集合基板用树脂进行间歇式密封。 切割部从密封树脂的顶表面形成到在电子部件模块的边界部分到达布置在基板中的接地电极的位置，以露出接地电极。 在侧表面和顶表面上施加导电膏。 然后，通过旋涂形成导电性薄膜，切断电子部件模块。

公开(公告)号：US20110136298A1

公开(公告)日：2011-06-09

申请号：US13026651

申请日：2011-02-14

Applicant: Katsumi KIKUCHI ,  Shintaro YAMAMICHI ,  Hideya MURAI ,  Takuo FUNAYA ,  Kentaro MORI ,  Takehiko MAEDA ,  Hirokazu HONDA ,  Kenta OGAWA ,  Jun TSUKANO

Inventor： Katsumi KIKUCHI ,  Shintaro YAMAMICHI ,  Hideya MURAI ,  Takuo FUNAYA ,  Kentaro MORI ,  Takehiko MAEDA ,  Hirokazu HONDA ,  Kenta OGAWA ,  Jun TSUKANO

IPC: H01L21/60 ,  H05K3/46

CPC classification number: H05K3/205 ,  H01L21/4857 ,  H01L21/486 ,  H01L21/563 ,  H01L23/498 ,  H01L23/49822 ,  H01L23/49827 ,  H01L24/45 ,  H01L24/48 ,  H01L24/73 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48228 ,  H01L2224/48472 ,  H01L2224/73203 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2224/92247 ,  H01L2924/00014 ,  H01L2924/01019 ,  H01L2924/01046 ,  H01L2924/01057 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01322 ,  H01L2924/09701 ,  H01L2924/12044 ,  H01L2924/181 ,  H01L2924/19041 ,  H05K3/244 ,  H05K3/423 ,  H05K2201/0338 ,  H05K2201/098 ,  H05K2201/09845 ,  H05K2203/0376 ,  H05K2203/0384 ,  H05K2203/0733 ,  H05K2203/1476 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/05599 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A wiring board has an insulating layer, a plurality of wiring layers formed in such a way as to be insulated from each other by the insulating layer, and a plurality of vias formed in the insulating layer to connect the wiring layers. Of the wiring layers, a surface wiring layer formed in one surface of the insulating layer include a first metal film exposed from the one surface and a second metal film embedded in the insulating layer and stacked on the first metal film. Edges of the first metal film project from edges of the second metal film in the direction in which the second metal film spreads. By designing the shape of the wiring layers embedded in the insulating layer in this manner, it is possible to obtain a highly reliable wiring board that can be effectively prevented from side etching in the manufacturing process and can adapt to miniaturization and highly dense packaging of wires.

Abstract translation: 布线基板具有绝缘层，多个布线层以通过绝缘层彼此绝缘的方式形成，以及形成在绝缘层中以连接布线层的多个通孔。 在布线层中，形成在绝缘层的一个表面上的表面布线层包括从一个表面露出的第一金属膜和嵌入在绝缘层中并叠放在第一金属膜上的第二金属膜。 第一金属膜的边缘沿着第二金属膜扩展的方向从第二金属膜的边缘突出。 通过以这种方式设计嵌入在绝缘层中的布线层的形状，可以获得在制造过程中可以有效地防止侧蚀刻的高可靠性布线板，并且可以适应电线的小型化和高密度封装 。