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    MIDDLE VOLTAGE TRANSISTOR AND FABRICATING METHOD OF THE SAME
    32.
    发明申请
    MIDDLE VOLTAGE TRANSISTOR AND FABRICATING METHOD OF THE SAME 有权

    公开(公告)号：US20250081573A1

    公开(公告)日：2025-03-06

    申请号：US18369815

    申请日：2023-09-18

    Applicant: UNITED MICROELECTRONICS CORP.

    Inventor： Shin-Hung Li

    IPC: H01L29/66 ,  H01L29/78

    Abstract: A middle voltage transistor structure includes a substrate. A gate structure is disposed on the substrate. A source lightly doped region and a drain lightly doped region are disposed within the substrate at two sides of the gate structure. A conductive structure contacts the lightly drain doped region. A first spacer surrounds the gate structure and a second spacer surrounds the conductive structure. The first spacer contacts the second spacer.

    SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME
    34.
    发明申请
    SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME 有权

    公开(公告)号：US20250072294A1

    公开(公告)日：2025-02-27

    申请号：US18946936

    申请日：2024-11-14

    Applicant: UNITED MICROELECTRONICS CORP.

    Inventor： Chia-Wei Liu ,  Jia-Feng Fang ,  Chun-Hsien Lin

    IPC: H10N50/01 ,  H10B61/00 ,  H10N50/80 ,  H10N50/85

    Abstract: A method for fabricating semiconductor device includes the steps of forming a magnetic tunneling junction (MTJ) stack on a substrate, performing an etching process to remove the MTJ stack for forming a MTJ, performing a deposition process to form a polymer on a sidewall of the MTJ, and removing the polymer to form a rough surface on the sidewall of the MTJ. Preferably, the MTJ could include a pinned layer on the substrate, a barrier layer on the pinned layer, and a free layer on the barrier layer, in which the rough surface could appear on sidewall of the pinned layer, sidewall of the barrier layer, and/or sidewall of the free layer.

    TRANSISTOR STRUCTURE
    35.
    发明申请
    TRANSISTOR STRUCTURE 有权

    公开(公告)号：US20250072071A1

    公开(公告)日：2025-02-27

    申请号：US18467739

    申请日：2023-09-15

    Applicant: United Microelectronics Corp.

    Inventor： Chih Wen Huang ,  Shih An Huang

    IPC: H01L29/10 ,  H01L29/06 ,  H01L29/78

    Abstract: A transistor structure includes a substrate, a first well region, a second well region, a gate structure, a drift region, a first doped region, a second doped region, and a first isolation structure. The first well region and the second well region are located in the substrate and adjacent to each other. The gate structure is located on the substrate. The drift region is located in the second well region on one side of the gate structure. The first doped region and the second doped region are located in the substrate on two sides of the gate structure. The first doped region is located in the first well region. The second doped region is located in the drift region. The first isolation structure is located in the substrate between the gate structure and the second doped region. The first well region has a first portion lower than a bottom surface of the drift region. The second well region has a second portion lower than the bottom surface of the drift region. A doping concentration of the first portion of the first well region is greater than a doping concentration of the second portion of the second well region.

    Anti-fuse memory
    38.
    发明授权
    Anti-fuse memory 有权

    公开(公告)号：US12237027B2

    公开(公告)日：2025-02-25

    申请号：US17966881

    申请日：2022-10-16

    Applicant: United Microelectronics Corp.

    Inventor： Chung-Hao Chen ,  Chi-Hsiu Hsu ,  Chi-Fa Lien ,  Ying-Ting Lin ,  Cheng-Hsiao Lai ,  Ya-Nan Mou

    IPC: G11C17/16 ,  G11C16/04 ,  G11C16/24

    Abstract: Provided is an anti-fuse memory including a anti-fuse memory cell including an isolation structure, a select gate, first and second gate insulating layers, an anti-fuse gate, and first, second and third doped regions. The isolation structure is disposed in a substrate. The select gate is disposed on the substrate. The first gate insulating layer is disposed between the select gate and the substrate. The anti-fuse gate is disposed on the substrate and partially overlapped with the isolation structure. The second gate insulating layer is disposed between the anti-fuse gate and the substrate. The first doped region and the second doped region are disposed in the substrate at opposite sides of the select gate, respectively, wherein the first doped region is located between the select gate and the anti-fuse gate. The third doped region is disposed in the substrate and located between the first doped region and the isolation structure.

    SONOS memory cell structure and fabricating method of the same
    40.
    发明授权
    SONOS memory cell structure and fabricating method of the same 有权

    公开(公告)号：US12225729B2

    公开(公告)日：2025-02-11

    申请号：US18608878

    申请日：2024-03-18

    Applicant: UNITED MICROELECTRONICS CORP.

    Inventor： Yung-Ting Chen ,  Hsueh-Chun Hsiao

    IPC: H10B43/30 ,  H01L21/28 ,  H01L29/423 ,  H01L29/66 ,  H01L29/792

    Abstract: An SONOS memory cell includes a silicon substrate. A tunnel silicon oxide layer, a silicon nitride layer and a silicon oxide layer are disposed from bottom to top on the silicon substrate. The silicon oxide layer includes two first silicon oxide layers and a second silicon oxide layer. A thickness of the silicon oxide layer is smaller than a thickness of each of the first silicon oxide layers. A control gate covers and contacts the silicon oxide layer. A first source/drain doping region and a second source/drain doping region are respectively disposed at two sides of the control gate. The silicon oxide layer has a cross section. The second silicon oxide layer is sandwiched between the two first silicon oxide layers on the cross section.

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