公开(公告)号：US12254353B2

公开(公告)日：2025-03-18

申请号：US17564092

申请日：2021-12-28

Applicant: Advanced Micro Devices, Inc. ,  ATI Technologies ULC

Inventor： Zhuo Chen ,  Steven J. Tovey

IPC: G06F9/50 ,  G06T1/20 ,  G06T1/60

Abstract: In order to efficiently process graphics data, operations are performed including allocating a first set of resource slots for a first execution instance of a pipeline shader program; correlating the first set of resource slots with graphics pipeline passes; and on a second execution instance of the pipeline shader program, assigning resource slots, from the first set of resource slots, to the graphics pipeline passes, based on the correlating.

公开(公告)号：US12254196B2

公开(公告)日：2025-03-18

申请号：US18057539

申请日：2022-11-21

Applicant: Advanced Micro Devices, Inc.

Inventor： Raul Gutierrez

IPC: G06F3/06

Abstract: Systems, apparatuses, and methods for moving data from a memory in a computing system to an I/O device. A system includes a processor, memory, I/O controller, and power management circuitry. An application stores data in the memory that is to be ultimately conveyed to an I/O device. The I/O controller is configured to convey the data to an I/O device according to a service interval. The I/O controller is configured to fetch a first data item from the memory stored by the application, and prefetch one or more additional data items from memory. The first data and prefetched data are stored in a locally accessible buffer of the I/O controller. The I/O controller is then configured to convey each of the first data and one or more data items from the buffer to the I/O device at regular intervals of time during a given period of time, prior to initiating a fetch of additional data from the memory. During the given period of time, the power management circuitry is configured to cause at least the memory to enter a reduced power state.

公开(公告)号：US12253892B2

公开(公告)日：2025-03-18

申请号：US17704912

申请日：2022-03-25

Applicant: Advanced Micro Devices, Inc.

Inventor： Jerry Anton Ahrens ,  William Robert Alverson ,  Amitabh Mehra ,  Grant Evan Ley ,  Anil Harwani ,  Joshua Taylor Knight

IPC: G06F1/20 ,  H05K5/02 ,  H05K5/03 ,  H05K7/20

Abstract: Package lids with carveouts configured for processor connection and alignment are described. Lid carveouts are configured to align and mechanically secure a cooling device to the package lid by receiving protrusions of the cooling device. Because the lid carveouts ensure precise alignment and orientation of a cooling device relative to a package lid, the lid design enables targeted cooling of discrete portions of the lid. Lid carveouts are further configured to expose one or more connectors disposed on a surface that supports package internal components. When contacted by corresponding connectors of a cooling device, the lid carveouts enable direct connections between the package and the attached cooling device. By creating a direct connection between package components and an attached cooling device, the lid carveouts enable a high-speed connection for proactive and on-demand cooling actuation.

公开(公告)号：US12248789B2

公开(公告)日：2025-03-11

申请号：US18309536

申请日：2023-04-28

Applicant: Advanced Micro Devices, Inc.

Inventor： Maxim V. Kazakov

IPC: G06F9/30 ,  G06F9/38

Abstract: Techniques are provided for executing wavefronts. The techniques include at a first time for issuing instructions for execution, performing first identifying, including identifying that sufficient processing resources exist to execute a first set of instructions together within a processing lane; in response to the first identifying, executing the first set of instructions together; at a second time for issuing instructions for execution, performing second identifying, including identifying that no instructions are available for which sufficient processing resources exist for execution together within the processing lane; and in response to the second identifying, executing an instruction independently of any other instruction.

公开(公告)号：US20250080471A1

公开(公告)日：2025-03-06

申请号：US18620838

申请日：2024-03-28

Applicant: Advanced Micro Devices, Inc.

Inventor： Rajshekhar BIRADAR

IPC: H04L47/36

Abstract: Embodiments herein describe creating multiple packet fragments from a large packet that, for example, exceeds a maximum transmission unit (MTU) supported by a network. In one embodiment, a network interface card or controller (NIC) replicates the large packet to form multiple copies (i.e., replicated packets). The number of replications can correspond to the number of fragments needed so the MTU is not exceeded. In one embodiment, the NIC assigns an identifier, such as an ID or a count value, to each replicated packet. The NIC can use the identifier to selectively remove portions of the payloads of the replicated packets (i.e., shrink the packets) so that the combined payloads (or union) of the packet fragments is the same as the payload in the large packet.

公开(公告)号：US20250079328A1

公开(公告)日：2025-03-06

申请号：US18242991

申请日：2023-09-06

Applicant: Advanced Micro Devices, Inc.

Inventor： Deepak Vasant KULKARNI ,  Sri Ranga Sai BOYAPATI ,  Rajen Singh SIDHU

IPC: H01L23/538 ,  H01L21/56 ,  H01L23/00 ,  H01L23/31 ,  H01L25/16

Abstract: Active and passive electronic components are placed on a substrate and encapsulated with mold material to produce a molded core substrate for fabricating a hybrid integrated circuit (IC) device. A carrier has a release film laminated to a face thereof. A seed layer of copper is added over the release film and fiducials are plated onto the copper seed layer for component placement using alignment marks on the fiducials. Mold material is applied to the encapsulation layer and around and over the components. Mold material is ground planar with component tops. The carrier and release film are removed, leaving the copper seed layer exposed, which is etched to a pattern. Holes are formed in the mold material and then surfaces thereof are copper plated. A multilayer dielectric film is laminated over copper plating. Vias are formed in the multilayer dielectric film for connections to components.

公开(公告)号：US20250077409A1

公开(公告)日：2025-03-06

申请号：US18240640

申请日：2023-08-31

Applicant: Advanced Micro Devices, Inc ,  ATI Technologies ULC

Inventor： Kishore Punniyamurthy ,  Richard David Sodke ,  Furkan Eris ,  Sergey Blagodurov ,  Bradford Michael Beckmann ,  Brandon Keith Potter ,  Khaled Hamidouche

IPC: G06F12/02 ,  G06F13/16

Abstract: A device includes a plurality of processing elements (PEs). A symmetric memory is allocated in each of the plurality of PEs. The device includes a switch connected to the plurality of PEs. The switch is to: receive, from a first processing element (PE) of the plurality of PEs, a message that includes a buffer offset, compute, based on the buffer offset, a first memory address of a first buffer in a first symmetric memory of the first PE and a second memory address of a second buffer in a second symmetric memory of a second PE of the plurality of PEs, and initiate, based on the first memory address and the second memory address, a direct memory access operation to access the first buffer and the second buffer.

公开(公告)号：US20250077320A1

公开(公告)日：2025-03-06

申请号：US18458571

申请日：2023-08-30

Applicant: Advanced Micro Devices, Inc.

Inventor： Nithya Viswanathan Shyla ,  Manu Shantharam

IPC: G06F9/54

Abstract: A message passing interface processing system is described. In accordance with message passing logic, a node selects an affinity domain for communication of data associated with a message passing interface and selects a first rank of a first process of the message passing interface assigned to a first partition of the affinity domain as a first partition leader rank and an affinity domain leader rank. The node selects a second rank of a second process of the message passing interface assigned to a second partition of the affinity domain as second partition leader rank, receives the data at the first partition leader rank, and communicates the data from the first partition leader rank to the second partition leader rank.

公开(公告)号：US12243576B2

公开(公告)日：2025-03-04

申请号：US18198709

申请日：2023-05-17

Applicant: Advanced Micro Devices, Inc.

Inventor： Jing Wang ,  Kedarnath Balakrishnan ,  Kevin M. Brandl ,  James R. Magro

IPC: G06F9/24 ,  G06F1/3203 ,  G06F9/4401 ,  G11C11/406

Abstract: A method for performing stutter of dynamic random access memory (DRAM) where a system on a chip (SOC) initiates bursts of requests to the DRAM to fill buffers to allow the DRAM to self-refresh is disclosed. The method includes issuing, by a system management unit (SMU), a ForceZQCal command to the memory controller to initiate the stutter procedure in response to receiving a timeout request, such as an SMU ZQCal timeout request, periodically issuing a power platform threshold (PPT) request, by the SMU, to the memory controller, and sending a ForceZQCal command prior to a PPT request to ensure re-training occurs after ZQ Calibration. The ForceZQCal command issued prior to PPT request may reduce the latency of the stutter. The method may further include issuing a ForceZQCal command prior to each periodic re-training.

公开(公告)号：US12237286B2

公开(公告)日：2025-02-25

申请号：US18455960

申请日：2023-08-25

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： Rahul Agarwal

IPC: H01L23/00 ,  H01L23/528

Abstract: A semiconductor package for high-speed die connections using a conductive insert, the semiconductor package comprising: a die; a plurality of redistribution layers; a conductive insert housed in a perforation through the plurality of redistribution layers; and a conductive bump conductively coupled to an input/output (I/O) connection point of the die via the conductive insert.