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    CHIP PACKAGE WITH TAMPER PREVENTION
    1.
    发明申请
    CHIP PACKAGE WITH TAMPER PREVENTION 有权

    公开(公告)号：US20250132270A1

    公开(公告)日：2025-04-24

    申请号：US18382973

    申请日：2023-10-23

    Applicant: Advanced Micro Devices, Inc.

    Inventor： Mohit ARORA ,  Deepak Vasant KULKARNI ,  Richard E. GEORGE ,  Terry Eugene RICHARDSON

    IPC: H01L23/00 ,  H01L25/00 ,  H01L25/065

    Abstract: A chip package includes a package substrate and an integrated circuit (IC) die disposed on the package substrate. The IC dies includes a security asset. The chip package also includes a glass based shield selectively disposed on the IC die and above the security asset. The glass based shield is configured to block access to the security asset. In some embodiments, the chip package includes an oxide layer disposed between the glass based shield and the IC die. In some embodiments, the chip package includes a detection module and a wire connecting the detection module to the glass based shield. The detection module is configured to generate and send a serial bit stream to the glass based shield. The detection module is also configured to monitor for changes in the serial bit stream returning from the glass based shield. Changes detected in the serial bit stream indicates the glass based shield has been tampered.

    CHIP PACKAGE WITH ACTIVE SILICON BRIDGE
    2.
    发明申请
    CHIP PACKAGE WITH ACTIVE SILICON BRIDGE 有权

    公开(公告)号：US20250149525A1

    公开(公告)日：2025-05-08

    申请号：US18615918

    申请日：2024-03-25

    Applicant: Advanced Micro Devices, Inc.

    Inventor： Deepak Vasant KULKARNI ,  Alan D. SMITH ,  Raja SWAMINATHAN

    IPC: H01L25/18 ,  H01L23/00 ,  H01L23/367 ,  H01L23/538 ,  H10B80/00

    Abstract: Disclosed herein are chip packages and electronic devices that utilized an active silicon bridge having a memory controller to interface between a logic device having at least one compute die and one or more memory stacks within a singular chip package. In one example, a chip package is provided that includes a substrate, a logic device, a memory stack, and an active silicon bridge. The logic device is disposed over the substrate. The logic device includes one or more compute dies. The memory stack is disposed over the substrate adjacent the logic device. The active silicon bridge has a first portion and a second portion. The first portion is disposed between the substrate and the logic device, while the second portion is disposed between the substrate and the memory stack.

    MOLDED CORE SUBSTRATE FOR EMBEDDING COMPONENTS
    3.
    发明申请
    MOLDED CORE SUBSTRATE FOR EMBEDDING COMPONENTS 有权

    公开(公告)号：US20250079328A1

    公开(公告)日：2025-03-06

    申请号：US18242991

    申请日：2023-09-06

    Applicant: Advanced Micro Devices, Inc.

    Inventor： Deepak Vasant KULKARNI ,  Sri Ranga Sai BOYAPATI ,  Rajen Singh SIDHU

    IPC: H01L23/538 ,  H01L21/56 ,  H01L23/00 ,  H01L23/31 ,  H01L25/16

    Abstract: Active and passive electronic components are placed on a substrate and encapsulated with mold material to produce a molded core substrate for fabricating a hybrid integrated circuit (IC) device. A carrier has a release film laminated to a face thereof. A seed layer of copper is added over the release film and fiducials are plated onto the copper seed layer for component placement using alignment marks on the fiducials. Mold material is applied to the encapsulation layer and around and over the components. Mold material is ground planar with component tops. The carrier and release film are removed, leaving the copper seed layer exposed, which is etched to a pattern. Holes are formed in the mold material and then surfaces thereof are copper plated. A multilayer dielectric film is laminated over copper plating. Vias are formed in the multilayer dielectric film for connections to components.

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