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    METHOD OF FABRICATING SUBSTRATE
    32.
    发明申请
    METHOD OF FABRICATING SUBSTRATE 有权
    制造基板的方法

    公开(公告)号：US20090197364A1

    公开(公告)日：2009-08-06

    申请号：US12422428

    申请日：2009-04-13

    Applicant: Tzyy-Jang Tseng ,  Chih-Ming Chang ,  Cheng-Po Yu ,  Chung W. Ho

    Inventor： Tzyy-Jang Tseng ,  Chih-Ming Chang ,  Cheng-Po Yu ,  Chung W. Ho

    IPC: H01L21/02 ,  H01L21/78

    CPC classification number: H01L23/142 ,  H01L21/6835 ,  H01L33/486 ,  H01L33/62 ,  H01L33/642 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/73265 ,  H01L2924/181 ,  H05K3/06 ,  H05K3/202 ,  H05K2201/09881 ,  H05K2203/0369 ,  H05K2203/1476 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2924/00014

    Abstract: A method of fabricating a substrate includes following steps. First, a metallic panel having a first surface and a second surface is provided. A first half-etching process is carried out to etch the first surface of the metallic panel to a first depth so that a first patterned metallic layer is formed on the first surface. Next, a first insulating material is deposited into gaps in the first patterned metallic layer to form a first insulator. Thereafter, a second half-etching process is carried out to etch the second surface of the metallic panel to a second depth and expose at least a portion of the first insulator so that a second patterned metallic layer is formed on the second surface. The first depth and the second depth together equal the thickness of the metallic panel.

    Abstract translation: 制造衬底的方法包括以下步骤。 首先，提供具有第一表面和第二表面的金属板。 执行第一半蚀刻工艺以将金属板的第一表面蚀刻到第一深度，使得在第一表面上形成第一图案化金属层。 接下来，将第一绝缘材料沉积在第一图案化金属层中的间隙中以形成第一绝缘体。 此后，执行第二半蚀刻工艺以将金属板的第二表面蚀刻到第二深度，并且暴露第一绝缘体的至少一部分，使得在第二表面上形成第二图案化金属层。 第一深度和第二深度一起等于金属面板的厚度。

    PROCESS OF FABRICATING CIRCUIT STRUCTURE
    33.
    发明申请
    PROCESS OF FABRICATING CIRCUIT STRUCTURE 有权
    制作电路结构的过程

    公开(公告)号：US20090104772A1

    公开(公告)日：2009-04-23

    申请号：US12345474

    申请日：2008-12-29

    Applicant: Cheng-Po Yu

    Inventor： Cheng-Po Yu

    IPC: H01L21/44 ,  H01L21/02

    CPC classification number: H05K1/116 ,  H01L21/6835 ,  H01L2221/68359 ,  H05K3/20 ,  H05K3/4644 ,  H05K3/4658 ,  H05K2201/09454 ,  H05K2201/09563 ,  H05K2201/096 ,  Y10T29/49124

    Abstract: A process for forming a circuit structure includes providing a first composite-layer structure at first. A second composite-layer structure is then provided. The first composite-layer structure, a second dielectric layer and the second composite-layer structure are pressed so that a second circuit pattern and an independent via pad are embedded in the second dielectric layer, and the second dielectric layer is connected to the first dielectric layer. A first carrier substrate and a second carrier substrate are removed to expose a first circuit pattern and the second circuit pattern. At least one first opening that passes through the second dielectric layer and exposes the independent via pad is formed, and the first opening is filled with a conductive material to form a second conductive via that connects the independent via pad and a second via pad.

    Abstract translation: 一种形成电路结构的工艺包括首先提供第一复合层结构。 然后提供第二复合层结构。 第一复合层结构，第二介电层和第二复合层结构被按压，使得第二电路图案和独立通孔焊盘嵌入第二电介质层中，并且第二电介质层连接到第一电介质层 层。 去除第一载体衬底和第二载体衬底以暴露第一电路图案和第二电路图案。 形成穿过第二电介质层并暴露独立通孔焊盘的至少一个第一开口，并且用导电材料填充第一开口以形成连接独立通孔焊盘和第二通孔焊盘的第二导电通孔。

    METHOD OF FORMING SOLDER MASK AND WIRING BOARD WITH SOLDER MASK
    34.
    发明申请
    METHOD OF FORMING SOLDER MASK AND WIRING BOARD WITH SOLDER MASK 有权
    用焊膏掩模形成焊接掩模和接线板的方法

    公开(公告)号：US20070099123A1

    公开(公告)日：2007-05-03

    申请号：US11307425

    申请日：2006-02-07

    Applicant: Tzyy-Jang Tseng ,  Cheng-Po Yu

    Inventor： Tzyy-Jang Tseng ,  Cheng-Po Yu

    IPC: G03C5/00

    CPC classification number: H05K3/28 ,  H05K3/3452 ,  H05K2203/013 ,  H05K2203/0557 ,  H05K2203/058 ,  H05K2203/1476

    Abstract: A method of forming solder mask, suitable for forming a solder mask on the surface of a wiring board, is provided. The surface of the wiring board includes a first region and a second region, and the surface of the wiring board has a wiring pattern thereon. The method includes forming a first sub solder mask in the first region on the surface of the wiring board by performing a screen-printing or a photolithographic process, and forming a second sub solder mask in the second region on the surface of the wiring board by performing an ink-jet printing process. The method not only improves the precision of the solder mask alignment on the wiring board and its reliability, but also increases the production rate and lowers the manufacturing cost.

    Abstract translation: 提供一种形成焊接掩模的方法，该方法适用于在布线板的表面上形成焊接掩模。 布线板的表面包括第一区域和第二区域，并且布线板的表面上具有布线图案。 该方法包括通过丝网印刷或光刻工艺在布线板的表面上的第一区域中形成第一子焊料掩模，并且在布线板的表面上的第二区域中形成第二副焊料掩模 进行喷墨打印处理。 该方法不仅提高了布线板上的焊盘对准的精度及其可靠性，而且提高了生产率，降低了制造成本。

    Circuit structure of circuit board
    35.
    发明授权
    Circuit structure of circuit board 有权
    电路板的电路结构

    公开(公告)号：US08466369B2

    公开(公告)日：2013-06-18

    申请号：US13305310

    申请日：2011-11-28

    Applicant: Cheng-Po Yu

    Inventor： Cheng-Po Yu

    IPC: H05K1/03

    CPC classification number: H05K3/107 ,  H05K1/0265 ,  H05K3/0032 ,  H05K3/06 ,  H05K3/061 ,  H05K2201/0376 ,  H05K2201/09727 ,  H05K2203/0369 ,  Y10T29/49117 ,  Y10T29/49126 ,  Y10T29/49155 ,  Y10T29/49165

    Abstract: A circuit structure of a circuit board includes a dielectric layer, a number of first circuits, and a number of second circuits. The dielectric layer has a surface and an intaglio pattern. The first circuits are disposed on the surface of the dielectric layer. The second circuits are disposed in the intaglio pattern of the dielectric layer. Line widths of the second circuits are smaller than line widths of the first circuits, and a distance between every two of the adjacent second circuits is shorter than a distance between every two of the adjacent first circuits.

    Abstract translation: 电路板的电路结构包括电介质层，多个第一电路和多个第二电路。 电介质层具有表面和凹版图案。 第一电路设置在电介质层的表面上。 第二电路设置在电介质层的凹版图案中。 第二电路的线宽小于第一电路的线宽，并且相邻的第二电路中的每两个之间的距离比相邻的第一电路中的每两个之间的距离短。

    PROCESS FOR FABRICATING WIRING BOARD
    36.
    发明申请
    PROCESS FOR FABRICATING WIRING BOARD 审中-公开
    制造布线板的工艺

    公开(公告)号：US20120174391A1

    公开(公告)日：2012-07-12

    申请号：US13423578

    申请日：2012-03-19

    Applicant: Tsung-Yuan Chen ,  Chun-Chien Chen ,  Cheng-Po Yu

    Inventor： Tsung-Yuan Chen ,  Chun-Chien Chen ,  Cheng-Po Yu

    IPC: H05K3/00

    CPC classification number: H05K3/428 ,  H05K3/0032 ,  H05K3/0035 ,  H05K3/0038 ,  H05K3/20 ,  H05K3/205 ,  H05K2201/09509 ,  H05K2201/09563 ,  H05K2201/0969 ,  H05K2203/0369 ,  H05K2203/0376 ,  H05K2203/0384 ,  H05K2203/0554 ,  H05K2203/108 ,  H05K2203/1476 ,  Y10T29/49124 ,  Y10T29/49126

    Abstract: A process for fabricating a wiring board is provided. In the process, a wiring carrying substrate including a carry substrate and a wiring layer is formed. Next, at least one blind via is formed in the wiring carrying substrate. Next, the wiring carrying substrate is laminated to another wiring carrying substrate via an insulation layer. The insulation layer is disposed between the wiring layers of the wiring carrying substrates and full fills the blind via. Next, parts of the carry substrates are removed to expose the insulation layer in the blind via. Next, a conductive pillar connected between the wiring layers is formed. Next, the rest carry substrates are removed.

    Abstract translation: 提供一种制造布线板的工艺。 在该过程中，形成包括携带衬底和布线层的布线承载衬底。 接下来，在布线承载基板中形成至少一个盲孔。 接下来，通过绝缘层将布线承载基板层叠到另一布线承载基板。 绝缘层设置在布线基板的布线层之间，并且完全填充盲孔。 接下来，去除部分搬运基板以露出盲孔中的绝缘层。 接下来，形成连接在布线层之间的导电柱。 接下来，其余的携带衬底被去除。

    Embedded wiring board and a manufacturing method thereof
    37.
    发明授权
    Embedded wiring board and a manufacturing method thereof 有权
    嵌入式布线板及其制造方法

    公开(公告)号：US08217278B2

    公开(公告)日：2012-07-10

    申请号：US12613072

    申请日：2009-11-05

    Applicant: Cheng-Po Yu

    Inventor： Cheng-Po Yu

    IPC: H05K1/11

    CPC classification number: H05K3/0035 ,  H05K3/107 ,  H05K3/465 ,  H05K2201/0236 ,  H05K2201/0959 ,  H05K2201/09845 ,  H05K2203/1476 ,  Y10T29/49155

    Abstract: An embedded wiring board includes an upper wiring layer, a lower wiring layer, an insulation layer, a first conductive pillar and a second conductive pillar. The upper wiring layer contains an upper pad, the lower wiring layer contains a lower pad, and the insulation layer contains an upper surface and a lower surface opposite to the upper surface. The upper pad is embedded in the upper surface and the lower pad is embedded in the lower surface. The first conductive pillar is located in the insulation layer and includes an end surface which is exposed by the upper surface. A height of the first conductive pillar relative to the upper surface is larger than a depth of the upper pad relative to the upper surface. In addition, the second conductive pillar is located in the insulation layer and is connected between the first conductive pillar and the lower pad.

    Abstract translation: 嵌入布线板包括上布线层，下布线层，绝缘层，第一导电柱和第二导电柱。 上布线层包含上焊盘，下布线层包含下焊盘，绝缘层包含与上表面相对的上表面和下表面。 上垫片嵌入在上表面中，下垫片嵌入下表面。 第一导电柱位于绝缘层中，并且包括由上表面暴露的端面。 第一导电柱相对于上表面的高度大于上垫相对于上表面的深度。 此外，第二导电柱位于绝缘层中并连接在第一导电柱和下垫之间。

    Circuit structure and process thereof
    39.
    发明授权
    Circuit structure and process thereof 有权
    电路结构及其工艺

    公开(公告)号：US07745933B2

    公开(公告)日：2010-06-29

    申请号：US11739515

    申请日：2007-04-24

    Applicant: Cheng-Po Yu

    Inventor： Cheng-Po Yu

    IPC: H01L23/48 ,  H01L23/52 ,  H01L29/40

    CPC classification number: H05K1/116 ,  H01L21/6835 ,  H01L2221/68359 ,  H05K3/20 ,  H05K3/4644 ,  H05K3/4658 ,  H05K2201/09454 ,  H05K2201/09563 ,  H05K2201/096 ,  Y10T29/49124

    Abstract: A circuit structure has a first dielectric layer, a first circuit pattern embedded in the first dielectric layer and having a first via pad, a first conductive via passing through the first dielectric layer and connecting to the first via pad, and an independent via pad disposed on a surface of the first dielectric layer away from the first via pad and connecting to one end of the first conductive via. The circuit structure further has a second dielectric layer disposed over the surface of the first dielectric layer where the independent via pad is disposed, a second conductive via passing through the second dielectric layer and connecting to the independent via pad, and a second circuit pattern embedded in the second dielectric layer, located at a surface thereof away from the independent via pad, and having a second via pad connected to the second conductive via.

    Abstract translation: 电路结构具有第一电介质层，第一电路图案，其嵌入在第一电介质层中并且具有第一通孔焊盘，穿过第一电介质层并连接到第一通孔焊盘的第一导电通孔和设置在第一电介质层上的独立通孔焊盘 在第一电介质层的远离第一通孔焊盘的表面上并连接到第一导电通孔的一端。 电路结构还具有设置在第一电介质层的表面上的第二电介质层，其中设置独立通孔焊盘，通过第二介电层并连接到独立通孔焊盘的第二导电通孔和嵌入的第二电路图案 在第二电介质层中，位于其远离独立通孔焊盘的表面，并且具有连接到第二导电通孔的第二通孔焊盘。

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