公开(公告)号：US5638402A

公开(公告)日：1997-06-10

申请号：US313384

申请日：1994-09-27

Applicant: Hideki Osaka ,  Toshihiko Ogura ,  Masao Inoue

Inventor： Hideki Osaka ,  Toshihiko Ogura ,  Masao Inoue

IPC: G06F3/00 ,  G06F13/00 ,  H04B3/00 ,  H04L25/00

CPC classification number: H04L25/0266

Abstract: A bus transceiver in a first signal processing circuit is connected to one end of a first bus connecting line for transferring a data pulse signal. A bus transceiver in a second signal processing circuit is connected to one end of a second bus connecting line for transferring a data pulse signal. Connected to the other end of the first bus connecting line is a first termination resistor. Connected to the other end of the second bus connecting line is a second termination resistor. In a portion of a predetermined length (parallel coupling portion) in the first and second bus connecting lines, the interval between the first and second bus connecting lines is held substantially constant so as to produce capacitive and inductive coupling between both the bus connecting lines. Each of the first and second bus transceivers includes a bus driver and a bus receiver. The bus receiver in the first bus transceiver generates a pulse signal substantially equal to an output pulse signal which was generated from the bus driver in the second bus transceiver, based on a pulse waveform induced in the parallel coupling portion on the first bus connecting line by the output pulse signal from the second bus transceiver.

Abstract translation: 第一信号处理电路中的总线收发器连接到用于传送数据脉冲信号的第一总线连接线的一端。 第二信号处理电路中的总线收发器连接到用于传送数据脉冲信号的第二总线连接线的一端。 连接到第一总线连接线的另一端是第一个终端电阻。 连接到第二总线连接线的另一端是第二个终端电阻。 在第一和第二总线连接线中的预定长度（平行耦合部分）的一部分中，第一和第二总线连接线之间的间隔保持基本上恒定，以便在两条总线连接线之间产生电容和电感耦合。 第一和第二总线收发器中的每一个包括总线驱动器和总线接收器。 第一总线收发器中的总线接收器基于在第一总线连接线上的并联耦合部分中感应的脉冲波形，产生基本上等于在第二总线收发器中的总线驱动器产生的输出脉冲信号的脉冲信号， 来自第二总线收发器的输出脉冲信号。

公开(公告)号：US20130132056A1

公开(公告)日：2013-05-23

申请号：US13702636

申请日：2011-05-13

Applicant: Tadanobu Toba ,  Kenichi Shimbo ,  Hidefumi Ibe ,  Hideki Osaka

Inventor： Tadanobu Toba ,  Kenichi Shimbo ,  Hidefumi Ibe ,  Hideki Osaka

IPC: G06F17/50

CPC classification number: G06F17/5036 ,  G01R31/31816 ,  G06F17/5022 ,  G06F2217/70

Abstract: A simulation apparatus includes a discrete events simulation section to perform a discrete type simulation of components of a configured model as defined based on attribute information that is information on parts of the components of the defined configured model and connection information showing a connectional relationship among the components of the defined configured model; and a soft error rate computation processing section to compute a soft error rate of the defined configured model based on the simulation result of the discrete events simulation section and data on soft error rates in the attribute information.

Abstract translation: 模拟装置包括：离散事件模拟部分，用于执行基于属性信息定义的配置模型的分量的离散类型模拟，所述属性信息是关于所定义的配置模型的组件的部分的信息，以及示出组件之间的连接关系的连接信息 的定义配置模型; 以及软错误率计算处理部，基于离散事件模拟部的模拟结果和属性信息中的软错误率的数据来计算定义的配置模型的软错误率。

公开(公告)号：US20110193215A1

公开(公告)日：2011-08-11

申请号：US13023565

申请日：2011-02-09

Applicant: Masahiro TOYAMA ,  Yutaka UEMATSU ,  Hideki OSAKA

Inventor： Masahiro TOYAMA ,  Yutaka UEMATSU ,  Hideki OSAKA

IPC: H01L23/50

CPC classification number: H01L23/50 ,  H01L23/49838 ,  H01L24/06 ,  H01L24/48 ,  H01L24/49 ,  H01L2224/05553 ,  H01L2224/05554 ,  H01L2224/05599 ,  H01L2224/06153 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/49112 ,  H01L2224/49175 ,  H01L2224/49433 ,  H01L2224/85399 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/01006 ,  H01L2924/01033 ,  H01L2924/014 ,  H01L2924/10162 ,  H01L2924/15311 ,  H01L2924/30107 ,  H01L2224/45099 ,  H01L2924/00

Abstract: Means for decreasing parasitic inductance by a realistic mounting method is provided. On a surface layer of a semiconductor package, there is provided a ground pad having a plurality of comb-tooth-shaped ground pads which are connecting points for wire bonding and are protruded on the surface layer of the semiconductor package. A power-supply pad is arranged between the comb-tooth-shaped ground pads. Two long and short ground wires are arranged in one comb-tooth-shaped ground pad. Also, two long and short power-supply wires are arranged in one power-supply pad. By arranging the long ground wire and the long power-supply wire so as to be parallel and close to each other and arranging the short power-supply wire and the short ground wire so as to be parallel and close to each other, the parasitic inductance is decreased.

Abstract translation: 提供了通过现实的安装方法来减小寄生电感的方法。 在半导体封装的表面层上，设置有多个梳齿形接地焊盘的接地焊盘，这些接地焊盘是用于引线接合的连接点，并且突出在半导体封装的表面层上。 在梳齿形接地垫之间设置电源垫。 两根长而短的接地线布置在一个梳齿形接地垫中。 此外，两个长短电源线布置在一个电源垫中。 通过将长接地线和长电源线布置为彼此并联并且将短电源线和短接地线布置成彼此并联并且彼此靠近，寄生电感 减少。

公开(公告)号：US07711817B2

公开(公告)日：2010-05-04

申请号：US12243081

申请日：2008-10-01

Applicant: Ryuichi Hattori ,  Toshihiko Ogura ,  Takashi Oeda ,  Koichi Okazawa ,  Hideki Osaka ,  Tsunehiro Tobita ,  Tsutomu Hara

Inventor： Ryuichi Hattori ,  Toshihiko Ogura ,  Takashi Oeda ,  Koichi Okazawa ,  Hideki Osaka ,  Tsunehiro Tobita ,  Tsutomu Hara

IPC: G06F15/173

CPC classification number: G06F9/5055 ,  G06F9/5044 ,  G06F2209/5015 ,  H04L29/12047 ,  H04L41/5009 ,  H04L61/15 ,  H04L67/36

Abstract: In each of the information processing apparatuses connected to each other via a network, there is arranged a quality of service (QOS) table to which functions and performance thereof are registered. When an information processing apparatus is additionally linked with the network, a QOS table thereof is automatically registered to a local directory of the network such that an agent converts the contents of the QOS table into service information to be supplied via a user interface to the user. Thanks to the operation, information of functions and performance of each information processing apparatus connected to the network is converted into service information for the user. Consequently, the user can much more directly receive necessary services.

Abstract translation: 在通过网络彼此连接的每个信息处理设备中，布置了其功能和性能被注册到其中的服务质量（QOS）表。 当信息处理设备另外与网络链接时，其QOS表被自动地注册到网络的本地目录，使得代理将QOS表的内容转换成要经由用户界面提供给用户的服务信息 。 由于操作，连接到网络的每个信息处理设备的功能和性能的信息被转换成用户的服务信息。 因此，用户可以更多地直接接收必要的服务。

公开(公告)号：US07319267B2

公开(公告)日：2008-01-15

申请号：US11712440

申请日：2007-03-01

Applicant: Yutaka Uematsu ,  Hideki Osaka ,  Yoji Nishio ,  Yukitoshi Hirose

Inventor： Yutaka Uematsu ,  Hideki Osaka ,  Yoji Nishio ,  Yukitoshi Hirose

IPC: H01L23/02 ,  H01L23/34

CPC classification number: H01L23/642 ,  H01L23/5223 ,  H01L23/5228 ,  H01L23/5286 ,  H01L23/647 ,  H01L25/105 ,  H01L2224/73204 ,  H01L2924/19105 ,  H01L2924/3011

Abstract: In a prior art, there has been a method in which a power supply line of an output buffer and that of a control circuit are independently provided so that the power supply noise occurring in the control circuit will not affect the output buffer. However, this method has had the problems that it increases both the number of power supply/grounding pins and power feed line inductance.The present invention provides a technique which, without causing the above two problems, i.e., (1) increased number of power supply/grounding pins and (2) increased power feed line inductance, prevents the noise causing a problem in a control circuit, from becoming routed around and induced into an output buffer. More specifically, the above can be realized by using either of two methods: (A) providing an on-chip bypass capacitor for the control circuit and isolating a power feed route of the control circuit from that of the output buffer in an AC-like manner, or (B) designing electrical parameters (inserting resistors) such that the oscillation mode of any electrical parameter noise induced into the power feed routes will change to overdamping.

Abstract translation: 在现有技术中，存在一种方法，其中独立地提供输出缓冲器的电源线和控制电路的电源线，使得控制电路中出现的电源噪声不会影响输出缓冲器。 然而，该方法存在增加电源/接地引脚数和馈电线电感的问题。 本发明提供一种技术，其不会引起上述两个问题，即（1）增加电源/接地引脚数量和（2）增加的馈电线电感，防止在控制电路中引起问题的噪声 变成路由并感应到输出缓冲区。 更具体地，可以通过以下两种方法之一来实现上述：（A）为控制电路提供片上旁路电容器，并将控制电路的馈电路径与AC类似的输出缓冲器的馈电路径隔离 方式或（B）设计电参数（插入电阻），使得引入馈电路径的任何电参数噪声的振荡模式将变为过阻尼。

公开(公告)号：US07257725B2

公开(公告)日：2007-08-14

申请号：US10294594

申请日：2002-11-15

Applicant: Hideki Osaka ,  Toyohiko Komatsu ,  Masashi Horiguchi ,  Susumu Hatano ,  Kazuya Ito

Inventor： Hideki Osaka ,  Toyohiko Komatsu ,  Masashi Horiguchi ,  Susumu Hatano ,  Kazuya Ito

IPC: G06F1/00

CPC classification number: G06F13/4086

Abstract: A clock is located at a position close to a plurality of memory modules connected to a memory controller and located away from the controller, and wiring is carried out so that read access is preferential for transmission of read data. With respect to write data, a delay amount corresponding to a round-trip propagation delay time to each of the modules is measured and writing of the write data is carried out while maintaining a known time relationship between the clock and data. To measure round-trip reflection, lines are wired between the modules and a location detection circuit in a 1:1 relationship, and the circuit measures a time taken from a signal output time of a driver having the same impedance as that of the wired lines to a reflected-wave reception time of a hysteresis receiver.

Abstract translation: 时钟位于靠近与存储器控制器并且远离控制器的多个存储器模块的位置，并且执行布线，使得读取访问优先于读取数据的传输。 对于写数据，测量对应于每个模块的往返传播延迟时间的延迟量，并且在保持时钟和数据之间的已知时间关系的同时执行写入数据的写入。 为了测量往返反射，线路以1：1的关系连接到模块和位置检测电路之间，并且电路测量从具有与有线线路相同阻抗的驱动器的信号输出时间所花费的时间 到滞后接收器的反射波接收时间。

公开(公告)号：US20060017144A1

公开(公告)日：2006-01-26

申请号：US10981676

申请日：2004-11-05

Applicant: Yutaka Uematsu ,  Hideki Osaka ,  Yoji Nishio ,  Yukitoshi Hirose

Inventor： Yutaka Uematsu ,  Hideki Osaka ,  Yoji Nishio ,  Yukitoshi Hirose

IPC: H01L23/02

CPC classification number: H01L23/642 ,  H01L23/5223 ,  H01L23/5228 ,  H01L23/5286 ,  H01L23/647 ,  H01L25/105 ,  H01L2224/73204 ,  H01L2924/19105 ,  H01L2924/3011

Abstract: The present invention provides a technique which, without causing two problems, i.e., (1) increased number of power supply/grounding pins and (2) increased power feed line inductance, prevents the noise causing a problem in a control circuit, from becoming routed around and induced into an output buffer. More specifically, the above can be realized by using either of two methods: (A) providing an on-chip bypass capacitor for the control circuit and isolating a power feed route of the control circuit from that of the output buffer in an AC-like manner, or (B) designing electrical parameters (inserting resistors) such that the oscillation mode of any electrical parameter noise induced into the power feed routes will change to overdamping.

Abstract translation: 本发明提供一种技术，其不会引起两个问题，即（1）增加电源/接地引脚的数量和（2）增加的馈电线电感，防止在控制电路中引起问题的噪声变为布线 并引入输出缓冲区。 更具体地，可以通过以下两种方法之一来实现上述：（A）为控制电路提供片上旁路电容器，并将控制电路的馈电路径与AC类似的输出缓冲器的馈电路径隔离 方式或（B）设计电参数（插入电阻），使得引入馈电路径的任何电参数噪声的振荡模式将变为过阻尼。

公开(公告)号：US06985111B2

公开(公告)日：2006-01-10

申请号：US10717192

申请日：2003-11-20

Applicant: Tsutomu Hara ,  Takashi Matsumoto ,  Hideki Osaka ,  Hitoshi Yokota ,  Kenji Kashiwagi

Inventor： Tsutomu Hara ,  Takashi Matsumoto ,  Hideki Osaka ,  Hitoshi Yokota ,  Kenji Kashiwagi

IPC: H01Q1/24

CPC classification number: H01Q1/526 ,  H05K1/0218 ,  H05K1/0237 ,  H05K1/141 ,  H05K2201/09309 ,  H05K2201/09618

Abstract: A printed circuit board with reduced noise effects and without the need to increase the distance between a noise source and a wireless communication board. The circuit board includes multilayer structural conductive layers having a first conductive plane connected to power supply potential and a second conductive plane connected to ground potential. The first and second conductive planes are formed such that an electric field generated by a potential difference between the first conductive plane and the second conductive plane is concentrated on one side of one of the first conductive plane and the second conductive plane. The conductive plane associated with the concentrated electric field and the wireless communication board are on different sides relative to the conductive plane that is not associated with the concentrated electric field.

Abstract translation: 一种印刷电路板，具有降低的噪音影响，无需增加噪声源与无线通信板之间的距离。 电路板包括具有连接到电源电位的第一导电平面和连接到地电势的第二导电平面的多层结构导电层。 第一和第二导电平面形成为使得由第一导电平面和第二导电平面之间的电位差产生的电场集中在第一导电平面和第二导电平面之一的一侧。 与集中电场相关联的导电平面和无线通信板相对于与集中电场不相关的​​导电平面在不同的一侧。

公开(公告)号：US06978328B1

公开(公告)日：2005-12-20

申请号：US09570349

申请日：2000-05-12

Applicant: Hideki Osaka ,  Takashi Tsunehiro ,  Koichi Kimura ,  Susumu Hatano ,  Kazuya Ito ,  Toshio Sugano ,  Toyohiko Komatsu

Inventor： Hideki Osaka ,  Takashi Tsunehiro ,  Koichi Kimura ,  Susumu Hatano ,  Kazuya Ito ,  Toshio Sugano ,  Toyohiko Komatsu

IPC: G06F3/00 ,  G06F1/00 ,  G06F12/00 ,  G06F13/16 ,  H01P5/00 ,  H01P5/18 ,  H05K1/00 ,  H05K1/02 ,  H05K1/14

CPC classification number: H05K1/0246 ,  H05K1/0228 ,  H05K1/0298 ,  H05K1/14 ,  H05K2201/044 ,  H05K2201/09236 ,  H05K2201/09627 ,  H05K2201/10022

Abstract: A bus system for carrying out data transfer between one bus master and a plurality of bus slaves. The bus system includes plural directional couplers which are formed by arranging respective parts of lines drawn from the bus slaves, without being in contact with, in the neighborhood of, and in parallel with a line drawn from the bus master. The line drawn from the bus master to a terminating resistance is wired to be folded. The directional couplers are further formed by arranging parts of the lines drawn from the bus slaves alternatively with respect to a first line part of the line drawn from the bus master ranging from the bus master to a fold of the line drawn from the bus master and with respect to a second line part of the line drawn from the bus master ranging from the fold to the terminating resistance.

Abstract translation: 一种用于在一个总线主机和多个总线从站之间执行数据传输的总线系统。 总线系统包括多个定向耦合器，其通过布置从总线从站引出的线的相应部分而形成，而不与从总线主控板引出的线相邻并且平行。 从总线主站到终端电阻的线被布线以折叠。 定向耦合器还通过将从总线主机引出的线路的一部分相对于从总线主机从总线主机抽出的线的第一线部分交替地排列成从总线主机引出的线的一部分， 相对于从总线主线抽出的从折叠到终止电阻的线的第二线部分。

公开(公告)号：US06766404B1

公开(公告)日：2004-07-20

申请号：US09568055

申请日：2000-05-10

Applicant: Hideki Osaka ,  Akira Yamagiwa ,  Kenichi Ishibashi

Inventor： Hideki Osaka ,  Akira Yamagiwa ,  Kenichi Ishibashi

IPC: G06F100

CPC classification number: H04L25/0278 ,  G06F13/4077

Abstract: A fast transfer bus system capable of fast data transfer with no reflection at branch points. Four LSIs having constant-impedance interfaces are connected via two variable resistors each having three signal terminals. A variable impedance LSI is connected between these variable resistors. When the LSIs connected to the variable resistor do not work as a bus driver, three variable resistance elements in each variable resistor are set to have a value of ⅓ of the characteristic impedance Zo of connection lines, and are connected in a Y-letter shape. When one of LSIs connected to the variable resistor works as a bus driver, the values of the variable resistance elements are set to low impedance or Zo.

Abstract translation: 快速传输总线系统，能够快速传输数据，在分支点无反射。 具有恒定阻抗接口的四个LSI通过两个可变电阻器连接，每个可变电阻器具有三个信号端子。 可变阻抗LSI连接在这些可变电阻之间。 当连接到可变电阻器的LSI不能用作总线驱动器时，每个可变电阻器中的三个可变电阻元件被设置为连接线的特性阻抗Zo的1/3，并且以Y- 字母形状。 当连接到可变电阻器的LSI中的一个作为总线驱动器工作时，可变电阻元件的值被设置为低阻抗或Zo。