CIRCUIT FOR OPTOELECTRONIC DOWN-CONVERSION OF THZ SIGNALS

    公开(公告)号:US20220077603A1

    公开(公告)日:2022-03-10

    申请号:US17466908

    申请日:2021-09-03

    Abstract: A circuit for optoelectronic down-conversion of a terahertz, THz, signal comprises a first photodiode and a second photodiode configured to be excited by an optical beat signal. The photodiodes are coupled in series through a common antenna. The terminals of the antenna are coupled to form an output terminal and the antenna is configured to receive the terahertz, THz, signal. The photodiodes thereby, via the optical beat signal, respectively, down-convert the THz signal and generate a current comprising an intermediate frequency, IF, component and a direct current, DC, component. The respective generated currents are summed at the output terminal, thereby obtaining the IF components and cancelling the DC components.

    Stacked segmented power amplifier circuitry and a method for controlling a stacked segmented power amplifier circuitry

    公开(公告)号:US11223329B2

    公开(公告)日:2022-01-11

    申请号:US16788696

    申请日:2020-02-12

    Abstract: A power amplifier circuitry (100) comprises: a transistor stack (110) comprising at least two stacked transistor units (112A, 112B, 112C) for amplifying input signals; wherein each stacked transistor unit (112A, 112B, 112C) comprises a plurality of controllable segments (120-1 to 120-N, 130-1 to 130-N, 140-1 to 140-N), each comprising a segment transistor (122, 132, 142), wherein source terminals (123, 133, 143) within each transistor unit are connected, drain terminals (125, 135, 145) within each transistor unit are connected and gate terminals (124, 134, 144) within each transistor unit are connected, wherein each segment transistor (122, 132, 142) further comprises a back gate terminal (126, 136, 146) for setting a body bias, wherein at least two of the segment transistors (122, 132, 142) within each transistor unit have independently connected back gate terminals (126, 136, 146); and a control unit (190) configured to control the body bias for selecting an amplifier class of each of the controllable segments (120-1 to 120-N, 130-1 to 130-N, 140-1 to 140-N) of each of the stacked transistor units (112A, 112B, 112C).

    Light-to-digital converter
    33.
    发明申请

    公开(公告)号:US20200375484A1

    公开(公告)日:2020-12-03

    申请号:US16886714

    申请日:2020-05-28

    Abstract: A light-to-digital converter (2) comprises a light-to-current converter (10); a current integrator (4) with an integrator output (30) resettable to a baseline level; and a counter (18) with a digital output (26), wherein the light-to-current converter (10) is switchably connectable as a positive integration input to the current integrator (4), for, during a light-collecting phase (404-406), integrating a current from the light-to-current converter (10), the integrator output (30) starting from the baseline value and ending at a value to be digitized; a reference current source (14) is switchably connectable as a negative integration input to the current integrator (4), for, during a counting phase (406-408) subsequent to the light-collecting phase (404-406), integrating a reference current from the reference current source (14), the integrator output (30) starting from the value to be digitized and ending at the baseline value, the time spent integrating the reference current corresponding to the value to be digitized; and the counter (18) is configured for measuring the time.

    DTC-based PLL and method for operating the DTC-based PLL

    公开(公告)号:US10200047B2

    公开(公告)日:2019-02-05

    申请号:US15605261

    申请日:2017-05-25

    Abstract: The disclosure provides a phase locked loop, PLL, for phase locking an output signal to a reference signal. The PLL comprises a reference path providing the reference signal to a first input of a phase detector, a feedback loop providing the output signal of the PLL as a feedback signal to a second input of the phase detector, a controllable oscillator generating the output signal based on at least a phase difference between reference and feedback signal, a digital-to-time converter, DTC, delaying a signal that is provided at one of the first and second input, a delay calculation path for calculating a DTC delay value. The PLL further comprises a randomization unit for generating and adding a random offset, i.e. a pseudo-random integer, to the delay value. The offset is such that a target output of the phase detector remains substantially unchanged.

    Sensor, System, and Holder Arrangement for Biosignal Activity Measurement

    公开(公告)号:US20170172447A1

    公开(公告)日:2017-06-22

    申请号:US15382381

    申请日:2016-12-16

    Abstract: The disclosure relates to a sensor, a system, and a holder arrangement for biosignal activity measurement. One example embodiment includes a sensor module for brain activity measurement. The sensor module includes a main electrode base. The sensor module also includes a plurality of pins protruding from the main electrode base. The plurality of pins is arranged such that, when applied on a subject, the pins make contact with skin of the subject or are in close proximity with the skin of the subject. The main electrode base comprises electronic circuitry for near infrared spectroscopy (NIRS) measurements and electronic circuitry for electroencephalography (EEG) measurements, both connected to the plurality of pins. The plurality of pins includes electrically conductive pins. The plurality of pins also includes at least one source waveguide pin configured for light emitting purposes or at least one detector waveguide pin configured for light detection purposes.

    Circuit for digitizing a sum of signals
    38.
    发明授权
    Circuit for digitizing a sum of signals 有权
    用于数字化信号总和的电路

    公开(公告)号:US08963754B2

    公开(公告)日:2015-02-24

    申请号:US14022351

    申请日:2013-09-10

    CPC classification number: H03M3/32 H03M3/426 H03M3/452

    Abstract: A circuit for digitizing a sum of a first input signal and a plurality of second input signals has a passive adder that sums the second input signals and outputs a summation signal and a multi-bit quantizer circuit. The quantizer circuit compares the summation signal at a first comparator input with a signal at a second comparator input, which is derived from the first input signal and has an appropriate polarity so that the difference between the summation signal and the signal at the second comparator input is indicative of the sum of the first input signal and the plurality of second input signals. The comparator also produces a comparator output signal based on the sum of the first input signal and the plurality of second input signals. The quantizer circuit also has a control logic block for determining a multi-bit representation of the sum from the comparator output signal.

    Abstract translation: 用于对第一输入信号和多个第二输入信号的和进行数字化的电路具有对第二输入信号求和并输出求和信号和多位量化器电路的无源加法器。 量化器电路将第一比较器输入端的求和信号与第二比较器输入端的信号进行比较,该第二比较器输入端从第一输入信号导出,并具有适当的极性,使得求和信号与第二比较器输入端的信号之间的差值 表示第一输入信号和多个第二输入信号的和。 比较器还基于第一输入信号和多个第二输入信号的和产生比较器输出信号。 量化器电路还具有用于确定来自比较器输出信号的和的多位表示的控制逻辑块。

    METHOD, COMPUTER PROGRAM PRODUCT, AND DEVICE FOR ANALYZING A SPECKLE PATTERN FROM BIOLOGICAL TISSUE

    公开(公告)号:US20250140386A1

    公开(公告)日:2025-05-01

    申请号:US18914585

    申请日:2024-10-14

    Abstract: According to an aspect of the present inventive concept there is provided a method for analyzing a speckle pattern from biological tissue, the method comprising: receiving a time sequence of images of the speckle pattern, wherein each image of the time sequence of images comprises a plurality of elements; and for each respective image of the time sequence of images: applying a digital spatial filter procedure to the image for enhancing areas in the image corresponding to speckles of the speckle pattern, thereby generating a filtered image wherein a morphology of speckles of the speckle pattern is enhanced by compensation for variations in light intensity in the image; and analyzing the filtered image to determine a speckle pattern value representing an amount of distinguishable speckles of the speckle pattern in at least one region of the filtered image.

    Controlling Neuron Firing in a Spiking Neural Network

    公开(公告)号:US20240202506A1

    公开(公告)日:2024-06-20

    申请号:US18541268

    申请日:2023-12-15

    CPC classification number: G06N3/049

    Abstract: The present disclosure relates to a computer-implemented method for controlling the firing of neurons within a neuron layer of a spiking neural network. The method includes, by a handshake controller associated with the neuron layer, receiving a request for firing the neurons and, in response, generating a tick signal. The method further comprising, by the respective neurons, updating a neuron state when receiving a neuron input; and upon receiving the tick signal, by the respective neurons, firing the respective neurons that fulfil a firing condition based on the neuron state.

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