公开(公告)号：US07135406B2

公开(公告)日：2006-11-14

申请号：US10983681

申请日：2004-11-09

Applicant: Jian-Hong Lin ,  Ying-Jen Kao ,  Jye-Yen Cheng

Inventor： Jian-Hong Lin ,  Ying-Jen Kao ,  Jye-Yen Cheng

IPC: H01L21/44 ,  H01L21/4763

CPC classification number: H01L21/76808

Abstract: Methods for forming openings in damascene structures, such as dual damascene structures are provided, using plug materials having varied etching rates. In one embodiment, a semiconductor substrate is provided with a low-k material layer formed thereabove, the low-k material layer having an upper surface and at least one via opening formed therethrough. A first plug material layer is formed over the low-k material layer and filled in the via opening, the first plug material layer having a first etching rate. The first plug material layer is etched back to form a first plug partially filling the via opening. A second plug material layer is formed over the low-k material layer and the first plug. The second plug material layer is etched back to form a second plug partially below the upper surface of the low-k material layer, the second plug material layer having a second etching rate higher than the first etching rate.

Abstract translation: 提供了在镶嵌结构中形成开口的方法，例如双镶嵌结构，使用具有不同蚀刻速率的塞子材料。 在一个实施例中，半导体衬底设置有形成在其上的低k材料层，低k材料层具有上表面和至少一个通孔形成。 第一插塞材料层形成在低k材料层上并填充在通孔中，第一插塞材料层具有第一蚀刻速率。 将第一插塞材料层回蚀刻以形成部分填充通孔开口的第一插头。 在低k材料层和第一插塞上形成第二插塞材料层。 第二插塞材料层被回蚀刻以在低k材料层的上表面部分下方形成第二插头，第二插塞材料层具有高于第一蚀刻速率的第二蚀刻速率。

公开(公告)号：US20120050658A1

公开(公告)日：2012-03-01

申请号：US13005538

申请日：2011-01-13

Applicant: Mien-Mien Cheng ,  Yi-Suei Liao ,  Jian-Hong Lin ,  Chien-Feng Chiu

Inventor： Mien-Mien Cheng ,  Yi-Suei Liao ,  Jian-Hong Lin ,  Chien-Feng Chiu

IPC: G02F1/1343

CPC classification number: G02F1/136259 ,  G02F2001/13606 ,  G02F2001/136263 ,  G02F2001/136272

Abstract: A display panel includes an active device array substrate, an opposite substrate, and a liquid crystal layer. The active device array substrate includes a substrate and further includes a pixel array, signal lines, and first and second repairing lines all disposed on the substrate. The signal lines electrically connect the pixel array. The first repairing line includes first and second line segments respectively located on first and second sides of the pixel array. The first side is substantially perpendicular to the second side. The first and second line segments are electrically connected. The second repairing line includes third and fourth line segments respectively located on third and second sides of the pixel array. The third side is substantially parallel to the first side. The fourth and third line segments are electrically connected. The opposite substrate above the active device array substrate does not cover the first and third line segments.

Abstract translation: 显示面板包括有源器件阵列衬底，相对衬底和液晶层。 有源器件阵列衬底包括衬底，并且还包括像素阵列，信号线以及全部设置在衬底上的第一和第二修复线。 信号线电连接像素阵列。 第一修复线包括分别位于像素阵列的第一和第二侧上的第一和第二线段。 第一侧基本垂直于第二侧。 第一和第二线段电连接。 第二修复线包括分别位于像素阵列的第三和第二侧上的第三和第四线段。 第三侧基本上平行于第一侧。 第四和第三线段电连接。 有源器件阵列衬底上方的相对衬底不覆盖第一和第三线段。

公开(公告)号：US20110108945A1

公开(公告)日：2011-05-12

申请号：US13007927

申请日：2011-01-17

Applicant: Chien-Jung Wang ,  Jian-Hong Lin

Inventor： Chien-Jung Wang ,  Jian-Hong Lin

IPC: H01L27/04

CPC classification number: H01L23/585 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor chip includes a seal ring adjacent to edges of the semiconductor chip; an opening extending from a top surface to a bottom surface of the seal ring, wherein the opening has a first end on an outer side of the seal ring and a second end on an inner side of the seal ring; and a moisture barrier having a sidewall parallel to a nearest side of the seal ring, wherein the moisture barrier is adjacent the seal ring and has a portion facing the opening.

Abstract translation: 半导体芯片包括与半导体芯片的边缘相邻的密封环; 从所述密封环的顶表面延伸到底表面的开口，其中所述开口具有在所述密封环的外侧上的第一端和所述密封环的内侧上的第二端; 以及具有平行于所述密封环的最近侧的侧壁的防潮屏障，其中所述防潮层邻近所述密封环并且具有面向所述开口的部分。

公开(公告)号：US07816256B2

公开(公告)日：2010-10-19

申请号：US11487741

申请日：2006-07-17

Applicant: Hsien-Wei Chen ,  Jian-Hong Lin ,  Tzu-Li Lee

Inventor： Hsien-Wei Chen ,  Jian-Hong Lin ,  Tzu-Li Lee

IPC: H01L21/4763

CPC classification number: H01L21/7682 ,  H01L21/76828 ,  H01L21/76829 ,  H01L2221/1047

Abstract: An interconnect structure of an integrated circuit having improved reliability and a method for forming the same are provided. The method includes providing a substrate, forming a dielectric layer overlying the substrate, performing a first shrinking process, wherein the dielectric layer shrinks and has a first shrinkage rate, forming a conductive feature in the dielectric layer after the step of performing the first shrinking process, and performing a second shrinking process after the step of forming the conductive feature, wherein the dielectric layer substantially shrinks and has a second shrinkage rate.

Abstract translation: 提供了具有改善的可靠性的集成电路的互连结构及其形成方法。 该方法包括提供衬底，形成覆盖在衬底上的电介质层，执行第一收缩过程，其中电介质层收缩并具有第一收缩率，在执行第一收缩过程的步骤之后在介电层中形成导电特征 并且在形成导电特征的步骤之后执行第二收缩过程，其中介电层基本上收缩并且具有第二收缩率。

公开(公告)号：US20090058434A1

公开(公告)日：2009-03-05

申请号：US11849836

申请日：2007-09-04

Applicant: Jian-Hong Lin ,  Chin Chuan Peng ,  Shou-Chung Lee ,  Chien-Jung Wang ,  Chien Shih Tsai ,  Bi-Ling Lin ,  Yi-Lung Cheng

Inventor： Jian-Hong Lin ,  Chin Chuan Peng ,  Shou-Chung Lee ,  Chien-Jung Wang ,  Chien Shih Tsai ,  Bi-Ling Lin ,  Yi-Lung Cheng

IPC: G01R27/00

CPC classification number: G01R31/2858 ,  G01R31/2853 ,  G01R31/2884 ,  H01L22/14 ,  H01L22/34 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method for measuring a property of interconnections is provided. The method includes the following steps. A plurality of interconnection test patterns are provided. A pad to which the plurality of interconnection test patterns are parallelly connected is formed. At least one resistor is formed between at least one of the plurality of interconnection test patterns and the pad. The property of the plurality of interconnection test patterns is measured by applying a current, a voltage and/or a mechanical stress to the pad.

Abstract translation: 提供了一种用于测量互连性质的方法。 该方法包括以下步骤。 提供多个互连测试图案。 形成多个互连测试图案并联连接的焊盘。 至少一个电阻器形成在所述多个互连测试图案中的至少一个与所述焊盘之间。 通过对焊盘施加电流，电压和/或机械应力来测量多个互连测试图案的性质。

公开(公告)号：US20060040065A1

公开(公告)日：2006-02-23

申请号：US10923057

申请日：2004-08-19

Applicant: Han-Chang Shih ,  Jian-Hong Lin ,  Wei-Jen Hsieh ,  Yi-Ying Tsai ,  Uei-Shin Chen

Inventor： Han-Chang Shih ,  Jian-Hong Lin ,  Wei-Jen Hsieh ,  Yi-Ying Tsai ,  Uei-Shin Chen

IPC: C23C14/00 ,  H01L21/4763

CPC classification number: C23C14/48 ,  C23C14/046 ,  C23C18/1879 ,  C23C18/38 ,  H01J37/32412 ,  H01L21/76859 ,  H01L21/76864 ,  H01L21/76874

Abstract: A method for surface activation on the metallization of electronic devices is provided. It uses plasma-immersion ion implantation and electroless plating to implant the seeds onto the diffusion barrier layer as catalyst for the electroless Cu plating to accomplish the ULSI interconnect metallization. It achieves electroless Cu plating in the deep 100 nm scaled line-width ULSI interconnect metallization by the Pd plasma implantation catalytic treatment. The method can fill the 100 nm line-width vias and trenches for gaining high quality electroless plated metal interconnects, and substitute for the traditional wet activation by SnCl2 and PdCl2 solution. For the plasma implanted seeds and electroless copper techniques, good Cu step coverage and gap-filling capability are observed in the trench and via metallization process with high adhesive strength. After thermal treatment, no obvious interfacial diffusion induced electric failure is found in the interface of the Cu/(implanted Pd)/TaN/FSG assembly. Good electric and interfacial structure reliability are observed in the process, too.

Abstract translation: 提供了一种用于电子设备的金属化表面活化的方法。 它使用等离子体浸没离子注入和无电镀来将种子植入到扩散阻挡层上，作为化学镀铜的催化剂，以实现ULSI互连金属化。 它通过Pd等离子体注入催化处理在深度为100nm的线宽ULSI互连金属化中实现无电镀铜。 该方法可以填充100nm的线宽通孔和沟槽，以获得高质量的无电镀金属互连，并且替代传统的通过SnCl 2 2和PdCl 2 2溶液的湿活化 。 对于等离子体植入种子和无电铜技术，在沟槽和通过金属化过程中观察到良好的Cu台阶覆盖和间隙填充能力，具有高的粘合强度。 热处理后，在Cu /（注入Pd）/ TaN / FSG组件的界面处没有发现明显的界面扩散引起的电气故障。 在此过程中也观察到良好的电气和界面结构的可靠性。

公开(公告)号：US08508503B2

公开(公告)日：2013-08-13

申请号：US13072803

申请日：2011-03-28

Applicant: Jian-Hong Lin ,  Wen-Rei Guo ,  Ching-Hua Chuang

Inventor： Jian-Hong Lin ,  Wen-Rei Guo ,  Ching-Hua Chuang

IPC: G06F3/041

CPC classification number: G06F3/041 ,  G02F1/13338 ,  G06F3/0412 ,  G06F3/0418

Abstract: A touch panel includes a touch sensor, a liquid crystal panel, and a reverse circuit. The reverse circuit receives common voltage ripples of the liquid crystal panel, and outputs reversed common voltage ripples after reversing the common voltage ripples. After the touch sensor receives the reversed common voltage ripples, the touch sensor outputs a sensing signal according to the reversed common voltage ripples.

Abstract translation: 触摸面板包括触摸传感器，液晶面板和反向电路。 反向电路接收液晶面板的公共电压波纹，并在反转公共电压纹波之后输出反向的公共电压纹波。 在触摸传感器接收到反向的公共电压波纹之后，触摸传感器根据反向的公共电压纹波输出感测信号。

公开(公告)号：US20120209406A1

公开(公告)日：2012-08-16

申请号：US13396491

申请日：2012-02-14

Applicant: Jian-Yu Chen ,  Chia-Chung WU ,  Wun-Ya Gao ,  Jian-Hong Lin

Inventor： Jian-Yu Chen ,  Chia-Chung WU ,  Wun-Ya Gao ,  Jian-Hong Lin

IPC: A61F2/66

CPC classification number: A61F2/66 ,  A61F2002/5003 ,  A61F2002/5007 ,  A61F2002/6621 ,  A61F2002/6664

Abstract: A foot plate device is connected to a prosthetic lower leg of an artificial foot, and includes a flexible foot plate. The foot plate has a front plate section, an inclined intermediate plate section extending rearwardly and upwardly from a rear end of the front plate section, and a rear plate section extending rearwardly from a rear end of the intermediate plate section and generally parallel to the front plate section. The front plate section has at least one open-ended slot formed vertically therethrough and extending across the front plate section along a longitudinal direction of the foot plate, so as to divide the front plate section into two force-receiving plate portions. The rear plate section is connected with the prosthetic lower leg.

Abstract translation: 脚板装置连接到人造脚的假肢小腿，并且包括柔性脚板。 脚踏板具有前板部分，从前板部分的后端向后并向上延伸的倾斜中间板部分，以及从中间板部分的后端向后延伸并且大致平行于前部的后板部分 板段。 前板部分具有至少一个垂直穿过的开口槽，沿着脚板的纵向方向延伸穿过前板部分，以将前板部分分成两个受力板部分。 后板部分与假肢小腿连接。

公开(公告)号：US08242576B2

公开(公告)日：2012-08-14

申请号：US11186581

申请日：2005-07-21

Applicant: Jian-Hong Lin ,  Kang-Cheng Lin ,  Tzu-Li Lee

Inventor： Jian-Hong Lin ,  Kang-Cheng Lin ,  Tzu-Li Lee

IPC: H01L23/52

CPC classification number: H01L23/5258 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor structure prevents energy that is used to blow a fuse from causing damage. The semiconductor structure includes a device, guard ring, and at least one protection layer. The device is constructed on the semiconductor substrate underneath the fuse. The seal ring, which surrounds the fuse, is constructed on at least one metal layer between the device and the fuse for confining the energy therein. The protection layer is formed within the seal ring, on at least one metal layer between the device and the fuse for shielding the device from being directly exposed to the energy.

Abstract translation: 半导体结构防止用于熔断保险丝的能量造成损坏。 半导体结构包括器件，保护环和至少一个保护层。 该器件构造在保险丝下方的半导体衬底上。 围绕熔丝的密封环构造在设备和保险丝之间的至少一个金属层上，以将能量限制在其中。 保护层形成在密封环内，在设备和保险丝之间的至少一个金属层上，用于屏蔽器件不会直接暴露于能量。

公开(公告)号：US08068577B2

公开(公告)日：2011-11-29

申请号：US12565226

申请日：2009-09-23

Applicant: Yi-Suei Liao ,  Jian-Hong Lin

Inventor： Yi-Suei Liao ,  Jian-Hong Lin

IPC: G11C19/00

CPC classification number: G11C19/28 ,  G09G2300/0408 ,  G09G2300/0417 ,  G09G2310/0286 ,  G09G2320/043 ,  G11C19/184

Abstract: The present invention relates to a pull-down control circuit and a shift register of using same. In one embodiment, the pull-down control circuit includes a release circuit and four transistors T4, T5, T6 and T7 electrically coupled to each other. The release circuit is adapted for causing the transistor T5 to be turned on and off alternately, thereby substantially reducing the stress thereon, improving the reliability and prolonging the lifetime of the shift register.

Abstract translation: 本发明涉及一种下拉控制电路和使用它的移位寄存器。 在一个实施例中，下拉控制电路包括释放电路和彼此电耦合的四个晶体管T4，T5，T6和T7。 释放电路适于使晶体管T5交替地导通和截止，从而大大降低其上的应力，提高可靠性并延长移位寄存器的寿命。