公开(公告)号：US20100052067A1

公开(公告)日：2010-03-04

申请号：US12424739

申请日：2009-04-16

Applicant: Peng-Fu Hsu ,  Kang-Cheng Lin ,  Kuo-Tai Huang

Inventor： Peng-Fu Hsu ,  Kang-Cheng Lin ,  Kuo-Tai Huang

IPC: H01L27/092 ,  H01L21/8234

CPC classification number: H01L27/092 ,  H01L21/823842 ,  H01L29/49 ,  H01L29/51

Abstract: The present disclosure provides a method of fabricating a semiconductor device. The method includes providing a semiconductor substrate having a first region and a second region, forming a high-k dielectric layer over the semiconductor substrate, forming a capping layer over the high-k dielectric layer in the first region, forming a first metal layer over capping layer in the first region and over the high-k dielectric in the second region, thereafter, forming a first gate stack in the first region and a second gate stack in the second region, protecting the first metal layer in the first gate stack while performing a treatment process on the first metal layer in the second gate stack, and forming a second metal layer over the first metal layer in the first gate stack and over the treated first metal layer in the second gate stack.

Abstract translation: 本公开提供了制造半导体器件的方法。 该方法包括提供具有第一区域和第二区域的半导体衬底，在半导体衬底上形成高k电介质层，在第一区域的高k电介质层上形成覆盖层，形成第一金属层 在第一区域中的覆盖层和第二区域中的高k电介质之上，然后在第一区域中形成第一栅极堆叠，在第二区域中形成第二栅极叠层，保护第一栅极叠层中的第一金属层，同时 对所述第二栅极堆叠中的所述第一金属层进行处理工艺，以及在所述第一栅极堆叠中的所述第一金属层上方以及所述第二栅极堆叠中经处理的第一金属层之上形成第二金属层。

公开(公告)号：US07312486B1

公开(公告)日：2007-12-25

申请号：US10189910

申请日：2002-07-05

Applicant: Kang-Cheng Lin ,  Chin-Chiu Hsia

Inventor： Kang-Cheng Lin ,  Chin-Chiu Hsia

IPC: H01L29/80

CPC classification number: H01L23/5222 ,  H01L21/3212 ,  H01L23/522 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Dishing is known to be a problem after CMP of dielectric layers in which the distribution of embedded metal is non-uniform. This problem has been solved by populating those areas where the density of embedded metal is low with unconnected regions that, instead of being uniformly filled with metal, are made up of metallic patterns whose combined area within a given region is about half the total area of the region itself. Two examples of such patterns are a line stripe pattern (similar to a parquet flooring tile) and a checker board pattern. Data is presented comparing the parasitic capacitances resulting from the use of patterns of this type relative to conventional solid patterns. The effect of aligning the regions so as to reduce their degree of overlap with wiring channels is also discussed.

Abstract translation: 已知在嵌入金属的分布不均匀的介电层的CMP的CMP之后，已经发现了抛光。 这个问题已经通过填充嵌入金属的密度低的区域来解决，其中未连接的区域代替均匀填充有金属，由金属图案组成，其中给定区域内的组合面积为 区域本身。 这种图案的两个示例是线条纹图案（类似于镶木地板瓦片）和棋盘图案。 提供的数据比较了使用这种类型的图案相对于常规固体图案产生的寄生电容。 还讨论了对准这些区域以减小其与布线通道重叠程度的效果。

公开(公告)号：US06348733B1

公开(公告)日：2002-02-19

申请号：US09655087

申请日：2000-09-05

Applicant: Kang-Cheng Lin

Inventor： Kang-Cheng Lin

IPC: H01L214763

CPC classification number: H01L21/76831 ,  H01L21/76808 ,  H01L21/76843 ,  H01L2221/1031

Abstract: An improved dual damascene structure, and process for manufacturing it, are described in which the via hole is first lined with a layer of silicon nitride prior to adding the diffusion barrier and copper. This allows use of a barrier layer that is thinner than normal (since the silicon nitride liner is an effective diffusion barrier) so that more copper may be included in the via hole, resulting in an improved conductance of the via. A key feature of the process that is used to make the structure is the careful control of the etching process. In particular, the relative selectivity of the etch between silicon oxide and silicon nitride must be carefully adjusted.

Abstract translation: 描述了改进的双镶嵌结构及其制造方法，其中在添加扩散阻挡层和铜之前，通孔首先衬有氮化硅层。 这允许使用比正常情况更薄的阻挡层（因为氮化硅衬垫是有效的扩散阻挡层），使得更多的铜可以包含在通孔中，导致通孔的电导率提高。 用于制造结构的工艺的一个关键特征是仔细控制蚀刻工艺。 特别地，必须仔细地调整氧化硅和氮化硅之间的蚀刻的相对选择性。

公开(公告)号：US5920772A

公开(公告)日：1999-07-06

申请号：US884577

申请日：1997-06-27

Applicant: Kang-Cheng Lin

Inventor： Kang-Cheng Lin

IPC: H01L21/336 ,  H01L29/786 ,  H01L21/84

CPC classification number: H01L29/66765 ,  H01L29/78669 ,  H01L29/78678

Abstract: The present invention discloses a hybrid polysilicon/amorphous silicon TFT device for switching a LCD and a method for fabrication wherein a n.sup.+ doped amorphous silicon layer is advantageously used as a mask during a laser annealing process such that only a selected portion of a hydrogenated amorphous silicon layer is converted to a crystalline structure while other portions retain their amorphous structure. As a result, a polysilicon TFT and at least one amorphous silicon TFT are formed in the same structure and the benefits of both a polysilicon TFT and amorphous silicon TFT such as a high charge current and a low leakage current are retained in the hybrid structure.

Abstract translation: 本发明公开了一种用于切换LCD的混合多晶硅/非晶硅TFT器件及其制造方法，其中在激光退火工艺期间有利地使用n +掺杂非晶硅层作为掩模，使得只有选定部分的氢化非晶硅 层转化为晶体结构，而其它部分保留其非晶结构。 结果，在相同的结构中形成多晶硅TFT和至少一个非晶硅TFT，并且在混合结构中保留诸如高充电电流和低漏电流的多晶硅TFT和非晶硅TFT的优点。

公开(公告)号：US5658808A

公开(公告)日：1997-08-19

申请号：US689781

申请日：1996-08-14

Applicant: Kang-Cheng Lin

Inventor： Kang-Cheng Lin

IPC: H01L21/336 ,  H01L21/84 ,  H01L29/786 ,  H01L21/265 ,  H01L21/70

CPC classification number: H01L29/78645 ,  H01L29/6675 ,  H01L29/66757 ,  H01L29/78621

Abstract: A method of fabricating a polycrystalline silicon thin-film transistor having two symmetrical lateral resistors is disclosed. Two sub-gates are formed along with a gate in the gate metal or polysilicon layer of the thin-film transistor. The two sub-gates that are located symmetrically on the two sides of the gate have equal distances to the gate. One sub-gate is near the drain of the thin film transistor and the other near the source. Two sections in the polycrystalline silicon layer of the thin film transistor are blocked by the two sub-gates and no impurity material is doped. The two undoped sections form the symmetrical lateral resistors of this invention. The lateral resistor near the drain decreases the electric field in the nearby depletion area when the thin-film transistor is switched off. The current leakage is reduced.

Abstract translation: 公开了一种制造具有两个对称横向电阻器的多晶硅薄膜晶体管的方法。 两个子栅极与薄膜晶体管的栅极金属或多晶硅层中的栅极一起形成。 对称地位于栅极两侧的两个子栅极具有与栅极相等的距离。 一个子栅极在薄膜晶体管的漏极附近，另一个靠近源极。 薄膜晶体管的多晶硅层中的两个部分被两个子栅极阻挡，并且不掺杂杂质材料。 两个未掺杂部分形成本发明的对称横向电阻器。 当薄膜晶体管关闭时，漏极附近的横向电阻减小了附近耗尽区域中的电场。 电流泄漏减少。

公开(公告)号：US08242576B2

公开(公告)日：2012-08-14

申请号：US11186581

申请日：2005-07-21

Applicant: Jian-Hong Lin ,  Kang-Cheng Lin ,  Tzu-Li Lee

Inventor： Jian-Hong Lin ,  Kang-Cheng Lin ,  Tzu-Li Lee

IPC: H01L23/52

CPC classification number: H01L23/5258 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor structure prevents energy that is used to blow a fuse from causing damage. The semiconductor structure includes a device, guard ring, and at least one protection layer. The device is constructed on the semiconductor substrate underneath the fuse. The seal ring, which surrounds the fuse, is constructed on at least one metal layer between the device and the fuse for confining the energy therein. The protection layer is formed within the seal ring, on at least one metal layer between the device and the fuse for shielding the device from being directly exposed to the energy.

Abstract translation: 半导体结构防止用于熔断保险丝的能量造成损坏。 半导体结构包括器件，保护环和至少一个保护层。 该器件构造在保险丝下方的半导体衬底上。 围绕熔丝的密封环构造在设备和保险丝之间的至少一个金属层上，以将能量限制在其中。 保护层形成在密封环内，在设备和保险丝之间的至少一个金属层上，用于屏蔽器件不会直接暴露于能量。

公开(公告)号：US08193586B2

公开(公告)日：2012-06-05

申请号：US12389535

申请日：2009-02-20

Applicant: Chien-Hao Chen ,  Hao-Ming Lien ,  Ssu-Yi Li ,  Jun-Lin Yeh ,  Kang-Cheng Lin ,  Kuo-Tai Huang ,  Chii-Horng Li ,  Chien-Hau Fei ,  Wen-Chih Yang ,  Jin-Aun Ng ,  Chi Hsin Chang ,  Chun Ming Lin ,  Harry Chuang ,  Chien-Liang Chen

Inventor： Chien-Hao Chen ,  Hao-Ming Lien ,  Ssu-Yi Li ,  Jun-Lin Yeh ,  Kang-Cheng Lin ,  Kuo-Tai Huang ,  Chii-Horng Li ,  Chien-Hau Fei ,  Wen-Chih Yang ,  Jin-Aun Ng ,  Chi Hsin Chang ,  Chun Ming Lin ,  Harry Chuang ,  Chien-Liang Chen

IPC: H01L21/02 ,  H01L21/8238

CPC classification number: H01L21/28088 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/7833

Abstract: The present disclosure provides a semiconductor device that includes a semiconductor substrate and a transistor formed in the substrate. The transistor includes a gate stack having a high-k dielectric and metal gate, a sealing layer formed on sidewalls of the gate stack, the sealing layer having an inner edge and an outer edge, the inner edge interfacing with the sidewall of the gate stack, a spacer formed on the outer edge of the sealing layer, and a source/drain region formed on each side of the gate stack, the source/drain region including a lightly doped source/drain (LDD) region that is aligned with the outer edge of the sealing layer.

Abstract translation: 本公开提供一种半导体器件，其包括半导体衬底和形成在衬底中的晶体管。 晶体管包括具有高k电介质和金属栅极的栅极堆叠，形成在栅极叠层的侧壁上的密封层，密封层具有内边缘和外边缘，内边缘与栅叠层的侧壁相接合 ，形成在密封层的外边缘上的隔离物和形成在栅极堆叠的每一侧上的源极/漏极区域，源极/漏极区域包括与外部电极对准的轻掺杂源极/漏极（LDD）区域 密封层的边缘。

公开(公告)号：US20120086085A1

公开(公告)日：2012-04-12

申请号：US13329877

申请日：2011-12-19

Applicant: Peng-Fu Hsu ,  Kang-Cheng Lin ,  Kuo-Tai Huang

Inventor： Peng-Fu Hsu ,  Kang-Cheng Lin ,  Kuo-Tai Huang

IPC: H01L27/092 ,  H01L21/28

CPC classification number: H01L27/092 ,  H01L21/823842 ,  H01L29/49 ,  H01L29/51

Abstract: The present disclosure provides a method of fabricating a semiconductor device. The method includes providing a semiconductor substrate having a first region and a second region, forming a high-k dielectric layer over the semiconductor substrate, forming a capping layer over the high-k dielectric layer in the first region, forming a first metal layer over capping layer in the first region and over the high-k dielectric in the second region, thereafter, forming a first gate stack in the first region and a second gate stack in the second region, protecting the first metal layer in the first gate stack while performing a treatment process on the first metal layer in the second gate stack, and forming a second metal layer over the first metal layer in the first gate stack and over the treated first metal layer in the second gate stack.

Abstract translation: 本公开提供了制造半导体器件的方法。 该方法包括提供具有第一区域和第二区域的半导体衬底，在半导体衬底上形成高k电介质层，在第一区域的高k电介质层上形成覆盖层，形成第一金属层 在第一区域中的覆盖层和第二区域中的高k电介质之上，然后在第一区域中形成第一栅极堆叠，在第二区域中形成第二栅极叠层，保护第一栅极叠层中的第一金属层，同时 对所述第二栅极堆叠中的所述第一金属层进行处理工艺，以及在所述第一栅极堆叠中的所述第一金属层上方以及所述第二栅极堆叠中经处理的第一金属层之上形成第二金属层。

公开(公告)号：US20110001194A1

公开(公告)日：2011-01-06

申请号：US12883241

申请日：2010-09-16

Applicant: Yong-Tian Hou ,  Peng-Fu Hsu ,  Jin Ying ,  Kang-Cheng Lin ,  K. T. Huang ,  Tze-Liang Lee

Inventor： Yong-Tian Hou ,  Peng-Fu Hsu ,  Jin Ying ,  Kang-Cheng Lin ,  K. T. Huang ,  Tze-Liang Lee

IPC: H01L27/092

CPC classification number: H01L21/823842 ,  H01L21/28044 ,  H01L21/28088 ,  H01L21/823835 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/7833 ,  H01L29/7843

Abstract: A semiconductor structure and methods for forming the same are provided. The semiconductor structure includes a first MOS device of a first conductivity type and a second MOS device of a second conductivity type opposite the first conductivity type. The first MOS device includes a first gate dielectric on a semiconductor substrate; a first metal-containing gate electrode layer over the first gate dielectric; and a silicide layer over the first metal-containing gate electrode layer. The second MOS device includes a second gate dielectric on the semiconductor substrate; a second metal-containing gate electrode layer over the second gate dielectric; and a contact etch stop layer having a portion over the second metal-containing gate electrode layer, wherein a region between the portion of the contact etch stop layer and the second metal-containing gate electrode layer is substantially free from silicon.

Abstract translation: 提供半导体结构及其形成方法。 半导体结构包括第一导电类型的第一MOS器件和与第一导电类型相反的第二导电类型的第二MOS器件。 第一MOS器件包括在半导体衬底上的第一栅极电介质; 在所述第一栅极电介质上的第一含金属的栅电极层; 以及位于第一含金属栅电极层上的硅化物层。 第二MOS器件包括半导体衬底上的第二栅极电介质; 在所述第二栅极电介质上方的第二含金属的栅电极层; 以及具有位于所述第二含金属栅电极层上的部分的接触蚀刻停止层，其中所述接触蚀刻停止层的所述部分和所述第二含金属栅电极层之间的区域基本上不含硅。

公开(公告)号：US07829949B2

公开(公告)日：2010-11-09

申请号：US12589421

申请日：2009-10-23

Applicant: Joshua Tseng ,  Kang-Cheng Lin ,  Ji-Yi Yang ,  Kuo-Tai Huang ,  Ryan Chia-Jen Chen

Inventor： Joshua Tseng ,  Kang-Cheng Lin ,  Ji-Yi Yang ,  Kuo-Tai Huang ,  Ryan Chia-Jen Chen

IPC: H01L27/092

CPC classification number: H01L21/823857 ,  H01L21/823842

Abstract: A metal gate/high-k dielectric semiconductor device provides an NMOS gate structure and a PMOS gate structure formed on a semiconductor substrate. The NMOS gate structure includes a high-k gate dielectric treated with a dopant impurity such as La and the high-k gate dielectric material of the PMOS gate structure is deficient of this dopant impurity and further includes a work function tuning layer over the high-k gate dielectric.