公开(公告)号：US20160322328A1

公开(公告)日：2016-11-03

申请号：US15205346

申请日：2016-07-08

Applicant: ZIPTRONIX, INC.

Inventor： Qin-Yi Tong ,  Gaius Gillman Fountain, JR. ,  Paul M. Enquist

IPC: H01L23/00 ,  H01L25/065 ,  H01L25/00

CPC classification number: H01L24/83 ,  H01L21/0206 ,  H01L21/2007 ,  H01L21/31105 ,  H01L21/31116 ,  H01L21/322 ,  H01L21/76251 ,  H01L24/26 ,  H01L24/75 ,  H01L25/0657 ,  H01L25/50 ,  H01L27/085 ,  H01L29/06 ,  H01L29/16 ,  H01L2224/8301 ,  H01L2224/8303 ,  H01L2224/83031 ,  H01L2224/8309 ,  H01L2224/83099 ,  H01L2224/8319 ,  H01L2224/8385 ,  H01L2224/83894 ,  H01L2224/83896 ,  H01L2224/83948 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01007 ,  H01L2924/01013 ,  H01L2924/01018 ,  H01L2924/0102 ,  H01L2924/01023 ,  H01L2924/01033 ,  H01L2924/01039 ,  H01L2924/0106 ,  H01L2924/01061 ,  H01L2924/01072 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01084 ,  H01L2924/01093 ,  H01L2924/0132 ,  H01L2924/05442 ,  H01L2924/07802 ,  H01L2924/10253 ,  H01L2924/10329 ,  H01L2924/14 ,  Y10S148/012 ,  Y10S438/974 ,  Y10T156/10 ,  Y10T156/1043 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01049 ,  H01L2924/01031 ,  H01L2924/3512 ,  H01L2924/00

Abstract: A method for bonding at low or room temperature includes steps of surface cleaning and activation by cleaning or etching. The method may also include removing by-products of interface polymerization to prevent a reverse polymerization reaction to allow room temperature chemical bonding of materials such as silicon, silicon nitride and SiO2. The surfaces to be bonded are polished to a high degree of smoothness and planarity. VSE may use reactive ion etching or wet etching to slightly etch the surfaces being bonded. The surface roughness and planarity are not degraded and may be enhanced by the VSE process. The etched surfaces may be rinsed in solutions such as ammonium hydroxide or ammonium fluoride to promote the formation of desired bonding species on the surfaces.

公开(公告)号：US09431368B2

公开(公告)日：2016-08-30

申请号：US15064467

申请日：2016-03-08

Applicant: ZIPTRONIX, INC.

Inventor： Paul M. Enquist ,  Gaius Gillman Fountain, Jr.

IPC: H01L21/58 ,  H01L23/00 ,  H01L21/20 ,  H01L21/683 ,  H01L21/768 ,  H01L21/822 ,  H01L23/13 ,  H01L23/36 ,  H01L23/48 ,  H01L23/538 ,  H01L25/065 ,  H01L25/16 ,  H01L25/00 ,  H01L27/06 ,  H01L21/762 ,  H01L23/552 ,  H01L25/18 ,  H01L27/146

CPC classification number: H01L24/08 ,  H01L21/187 ,  H01L21/2007 ,  H01L21/6835 ,  H01L21/76251 ,  H01L21/76898 ,  H01L21/8221 ,  H01L23/13 ,  H01L23/36 ,  H01L23/481 ,  H01L23/5384 ,  H01L23/5385 ,  H01L23/5389 ,  H01L23/552 ,  H01L24/24 ,  H01L24/26 ,  H01L24/27 ,  H01L24/30 ,  H01L24/48 ,  H01L24/80 ,  H01L24/82 ,  H01L24/83 ,  H01L24/94 ,  H01L25/0652 ,  H01L25/0655 ,  H01L25/0657 ,  H01L25/16 ,  H01L25/167 ,  H01L25/18 ,  H01L25/50 ,  H01L27/0688 ,  H01L27/14634 ,  H01L2221/6835 ,  H01L2221/68359 ,  H01L2221/68363 ,  H01L2223/6677 ,  H01L2224/0807 ,  H01L2224/08123 ,  H01L2224/1134 ,  H01L2224/16 ,  H01L2224/24011 ,  H01L2224/24225 ,  H01L2224/24226 ,  H01L2224/24227 ,  H01L2224/3005 ,  H01L2224/30104 ,  H01L2224/305 ,  H01L2224/48091 ,  H01L2224/48101 ,  H01L2224/48227 ,  H01L2224/48247 ,  H01L2224/80896 ,  H01L2224/81894 ,  H01L2224/8303 ,  H01L2224/83092 ,  H01L2224/83099 ,  H01L2224/8319 ,  H01L2224/83193 ,  H01L2224/83345 ,  H01L2224/83359 ,  H01L2224/8385 ,  H01L2224/83894 ,  H01L2224/83896 ,  H01L2224/83912 ,  H01L2224/83948 ,  H01L2224/9202 ,  H01L2224/9212 ,  H01L2225/06513 ,  H01L2225/06524 ,  H01L2225/06541 ,  H01L2225/06555 ,  H01L2225/06589 ,  H01L2924/00013 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01015 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01057 ,  H01L2924/01074 ,  H01L2924/01082 ,  H01L2924/0132 ,  H01L2924/014 ,  H01L2924/05442 ,  H01L2924/07802 ,  H01L2924/10253 ,  H01L2924/10329 ,  H01L2924/1305 ,  H01L2924/13062 ,  H01L2924/13063 ,  H01L2924/13064 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/1461 ,  H01L2924/15153 ,  H01L2924/15165 ,  H01L2924/19041 ,  H01L2924/19043 ,  H01L2924/30105 ,  H01L2924/30107 ,  H01L2924/3011 ,  H01L2924/3025 ,  H01L2924/351 ,  Y10S148/012 ,  Y10S438/977 ,  H01L2224/13099 ,  H01L2924/01049 ,  H01L2924/01031 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2224/8203 ,  H01L2224/821 ,  H01L2224/80001 ,  H01L2224/82

Abstract: A method may include the steps of directly bonding a semiconductor device having a substrate to an element; and removing a portion of the substrate to expose a remaining portion of the semiconductor device after bonding. The element may include one of a substrate used for thermal spreading, impedance matching or for RF isolation, an antenna, and a matching network comprised of passive elements. A second thermal spreading substrate may be bonded to the remaining portion of the semiconductor device. Interconnections may be made through the first or second substrates. The method may also include bonding a plurality of semiconductor devices to an element, and the element may have recesses in which the semiconductor devices are disposed.

Abstract translation: 一种方法可以包括将具有衬底的半导体器件直接接合到元件的步骤; 以及去除所述衬底的一部分以在结合之后露出所述半导体器件的剩余部分。 元件可以包括用于热扩散，阻抗匹配或RF隔离的衬底之一，天线以及由无源元件组成的匹配网络。 第二热扩散基板可以结合到半导体器件的其余部分。 互连可以通过第一或第二基底进行。 该方法还可以包括将多个半导体器件接合到元件，并且元件可以具有设置半导体器件的凹部。

公开(公告)号：US09385024B2

公开(公告)日：2016-07-05

申请号：US14474476

申请日：2014-09-02

Applicant: Ziptronix, Inc.

Inventor： Qin-Yi Tong ,  Paul M. Enquist ,  Anthony Scot Rose

IPC: H01L21/762 ,  B23K20/02 ,  H01L21/48 ,  H01L23/00 ,  H01L25/00

CPC classification number: H01L21/76251 ,  B23K20/02 ,  H01L21/481 ,  H01L24/09 ,  H01L24/11 ,  H01L24/12 ,  H01L24/16 ,  H01L24/28 ,  H01L24/32 ,  H01L24/73 ,  H01L24/81 ,  H01L24/83 ,  H01L24/89 ,  H01L24/90 ,  H01L25/50 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/13011 ,  H01L2224/13099 ,  H01L2224/13109 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/32145 ,  H01L2224/80801 ,  H01L2224/81011 ,  H01L2224/81013 ,  H01L2224/81014 ,  H01L2224/81136 ,  H01L2224/81143 ,  H01L2224/81193 ,  H01L2224/81208 ,  H01L2224/8121 ,  H01L2224/81801 ,  H01L2224/81815 ,  H01L2224/8183 ,  H01L2224/81894 ,  H01L2224/83095 ,  H01L2224/8319 ,  H01L2224/8334 ,  H01L2224/83801 ,  H01L2224/8383 ,  H01L2224/8384 ,  H01L2224/8385 ,  H01L2224/83894 ,  H01L2224/83895 ,  H01L2224/83907 ,  H01L2224/9202 ,  H01L2225/06513 ,  H01L2924/00013 ,  H01L2924/01003 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01018 ,  H01L2924/01019 ,  H01L2924/01022 ,  H01L2924/01023 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01039 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/0105 ,  H01L2924/0106 ,  H01L2924/01072 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/0132 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/07802 ,  H01L2924/10329 ,  H01L2924/12042 ,  H01L2924/1305 ,  H01L2924/14 ,  H01L2924/1532 ,  H01L2924/351 ,  Y10T29/49126 ,  H01L2924/3512 ,  H01L2924/00 ,  H01L2224/29099 ,  H01L2224/05644 ,  H01L2924/00014 ,  H01L2224/05664 ,  H01L2224/05669 ,  H01L2224/05124 ,  H01L2224/05147

Abstract: A bonded device structure including a first substrate having a first set of metallic bonding pads, preferably connected to a device or circuit, and having a first non-metallic region adjacent to the metallic bonding pads on the first substrate, a second substrate having a second set of metallic bonding pads aligned with the first set of metallic bonding pads, preferably connected to a device or circuit, and having a second non-metallic region adjacent to the metallic bonding pads on the second substrate, and a contact-bonded interface between the first and second set of metallic bonding pads formed by contact bonding of the first non-metallic region to the second non-metallic region. At least one of the first and second substrates may be elastically deformed.

公开(公告)号：US09184125B2

公开(公告)日：2015-11-10

申请号：US14064807

申请日：2013-10-28

Applicant: Ziptronix, Inc.

Inventor： Paul M. Enquist ,  Gaius Gillman Fountain

IPC: H01L23/498 ,  H01L21/20 ,  H01L25/00 ,  H01L21/768

CPC classification number: H01L25/0657 ,  H01L21/2007 ,  H01L21/6835 ,  H01L21/76898 ,  H01L23/49866 ,  H01L24/32 ,  H01L24/83 ,  H01L25/50 ,  H01L2221/68359 ,  H01L2224/29147 ,  H01L2224/29155 ,  H01L2224/83053 ,  H01L2224/83201 ,  H01L2225/06541 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method of integrating a first substrate having a first surface with a first insulating material and a first contact structure with a second substrate having a second surface with a second insulating material and a second contact structure. The first insulating material is directly bonded to the second insulating material. A portion of the first substrate is removed to leave a remaining portion. A third substrate having a coefficient of thermal expansion (CTE) substantially the same as a CTE of the first substrate is bonded to the remaining portion. The bonded substrates are heated to facilitate electrical contact between the first and second contact structures. The third substrate is removed after heating to provided a bonded structure with reliable electrical contacts.

Abstract translation: 一种将具有第一表面的第一衬底与第一绝缘材料和第一接触结构与具有第二表面的第二衬底与第二绝缘材料和第二接触结构集成的方法。 第一绝缘材料直接接合到第二绝缘材料上。 去除第一衬底的一部分以留下剩余部分。 具有与第一基板的CTE基本相同的热膨胀系数（CTE）的第三基板被结合到剩余部分。 粘合的基底被加热以促进第一和第二接触结构之间的电接触。 在加热之后移除第三衬底以提供具有可靠电接触的接合结构。

公开(公告)号：US09171756B2

公开(公告)日：2015-10-27

申请号：US14198723

申请日：2014-03-06

Applicant: Ziptronix, Inc.

Inventor： Paul M. Enquist ,  Gaius Gillman Fountain, Jr. ,  Qin-Yi Tong

IPC: H01L21/4763 ,  H01L21/768 ,  H01L23/48 ,  H01L23/00 ,  H01L25/065 ,  H01L25/00

CPC classification number: H01L21/76838 ,  H01L21/76898 ,  H01L23/481 ,  H01L24/02 ,  H01L24/81 ,  H01L24/94 ,  H01L24/97 ,  H01L25/0657 ,  H01L25/50 ,  H01L27/0688 ,  H01L2224/0401 ,  H01L2224/81121 ,  H01L2224/81201 ,  H01L2224/8123 ,  H01L2224/81801 ,  H01L2224/81894 ,  H01L2224/81931 ,  H01L2224/83894 ,  H01L2224/9202 ,  H01L2224/97 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2924/01002 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01007 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01018 ,  H01L2924/01019 ,  H01L2924/0102 ,  H01L2924/01022 ,  H01L2924/01023 ,  H01L2924/01027 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01042 ,  H01L2924/01046 ,  H01L2924/01049 ,  H01L2924/0105 ,  H01L2924/01055 ,  H01L2924/01059 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01077 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/05042 ,  H01L2924/10329 ,  H01L2924/12044 ,  H01L2924/14 ,  H01L2924/19043 ,  H01L2924/3025 ,  H01L2224/81

Abstract: A method of three-dimensionally integrating elements such as singulated die or wafers and an integrated structure having connected elements such as singulated dies or wafers. Either or both of the die and wafer may have semiconductor devices formed therein. A first element having a first contact structure is bonded to a second element having a second contact structure. First and second contact structures can be exposed at bonding and electrically interconnected as a result of the bonding. A via may be etched and filled after bonding to expose and form an electrical interconnect to interconnected first and second contact structures and provide electrical access to this interconnect from a surface. Alternatively, first and/or second contact structures are not exposed at bonding, and a via is etched and filled after bonding to electrically interconnect first and second contact structures and provide electrical access to interconnected first and second contact structure to a surface. Also, a device may be formed in a first substrate, the device being disposed in a device region of the first substrate and having a first contact structure. A via may be etched, or etched and filled, through the device region and into the first substrate before bonding and the first substrate thinned to expose the via, or filled via after bonding.

公开(公告)号：US20150303263A1

公开(公告)日：2015-10-22

申请号：US14754111

申请日：2015-06-29

Applicant: Ziptronix, Inc.

Inventor： Qin-Yi Tong ,  Gaius Gillman Fountain, JR. ,  Paul M. Enquist

IPC: H01L29/16 ,  H01L27/085 ,  H01L29/06

CPC classification number: H01L24/83 ,  H01L21/0206 ,  H01L21/2007 ,  H01L21/31105 ,  H01L21/31116 ,  H01L21/322 ,  H01L21/76251 ,  H01L24/26 ,  H01L24/75 ,  H01L25/0657 ,  H01L25/50 ,  H01L27/085 ,  H01L29/06 ,  H01L29/16 ,  H01L2224/8301 ,  H01L2224/8303 ,  H01L2224/83031 ,  H01L2224/8309 ,  H01L2224/83099 ,  H01L2224/8319 ,  H01L2224/8385 ,  H01L2224/83894 ,  H01L2224/83896 ,  H01L2224/83948 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01007 ,  H01L2924/01013 ,  H01L2924/01018 ,  H01L2924/0102 ,  H01L2924/01023 ,  H01L2924/01033 ,  H01L2924/01039 ,  H01L2924/0106 ,  H01L2924/01061 ,  H01L2924/01072 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01084 ,  H01L2924/01093 ,  H01L2924/0132 ,  H01L2924/05442 ,  H01L2924/07802 ,  H01L2924/10253 ,  H01L2924/10329 ,  H01L2924/14 ,  Y10S148/012 ,  Y10S438/974 ,  Y10T156/10 ,  Y10T156/1043 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01049 ,  H01L2924/01031 ,  H01L2924/3512 ,  H01L2924/00

Abstract: A method for bonding at low or room temperature includes steps of surface cleaning and activation by cleaning or etching. The method may also include removing by-products of interface polymerization to prevent a reverse polymerization reaction to allow room temperature chemical bonding of materials such as silicon, silicon nitride and SiO2. The surfaces to be bonded are polished to a high degree of smoothness and planarity. VSE may use reactive ion etching or wet etching to slightly etch the surfaces being bonded. The surface roughness and planarity are not degraded and may be enhanced by the VSE process. The etched surfaces may be rinsed in solutions such as ammonium hydroxide or ammonium fluoride to promote the formation of desired bonding species on the surfaces.

公开(公告)号：US09130021B2

公开(公告)日：2015-09-08

申请号：US14198723

申请日：2014-03-06

Applicant: Ziptronix, Inc.

Inventor： Paul M. Enquist ,  Gaius Gillman Fountain, Jr. ,  Qin-Yi Tong

IPC: H01L21/4763 ,  H01L21/768 ,  H01L23/48 ,  H01L23/00 ,  H01L25/065 ,  H01L25/00

Abstract: A method of three-dimensionally integrating elements such as singulated die or wafers and an integrated structure having connected elements such as singulated dies or wafers. Either or both of the die and wafer may have semiconductor devices formed therein. A first element having a first contact structure is bonded to a second element having a second contact structure. First and second contact structures can be exposed at bonding and electrically interconnected as a result of the bonding. A via may be etched and filled after bonding to expose and form an electrical interconnect to interconnected first and second contact structures and provide electrical access to this interconnect from a surface. Alternatively, first and/or second contact structures are not exposed at bonding, and a via is etched and filled after bonding to electrically interconnect first and second contact structures and provide electrical access to interconnected first and second contact structure to a surface. Also, a device may be formed in a first substrate, the device being disposed in a device region of the first substrate and having a first contact structure. A via may be etched, or etched and filled, through the device region and into the first substrate before bonding and the first substrate thinned to expose the via, or filled via after bonding.

公开(公告)号：US20140187040A1

公开(公告)日：2014-07-03

申请号：US14198723

申请日：2014-03-06

Applicant: Ziptronix, Inc.

Inventor： Paul M. ENQUIST ,  Gaius Gillman Fountain, JR. ,  Qin-Yi Tong

IPC: H01L21/768

CPC classification number: H01L21/76838 ,  H01L21/76898 ,  H01L23/481 ,  H01L24/02 ,  H01L24/81 ,  H01L24/94 ,  H01L24/97 ,  H01L25/0657 ,  H01L25/50 ,  H01L27/0688 ,  H01L2224/0401 ,  H01L2224/81121 ,  H01L2224/81201 ,  H01L2224/8123 ,  H01L2224/81801 ,  H01L2224/81894 ,  H01L2224/81931 ,  H01L2224/83894 ,  H01L2224/9202 ,  H01L2224/97 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2924/01002 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01007 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01018 ,  H01L2924/01019 ,  H01L2924/0102 ,  H01L2924/01022 ,  H01L2924/01023 ,  H01L2924/01027 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01042 ,  H01L2924/01046 ,  H01L2924/01049 ,  H01L2924/0105 ,  H01L2924/01055 ,  H01L2924/01059 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01077 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/05042 ,  H01L2924/10329 ,  H01L2924/12044 ,  H01L2924/14 ,  H01L2924/19043 ,  H01L2924/3025 ,  H01L2224/81

Abstract: A method of three-dimensionally integrating elements such as singulated die or wafers and an integrated structure having connected elements such as singulated dies or wafers. Either or both of the die and wafer may have semiconductor devices formed therein. A first element having a first contact structure is bonded to a second element having a second contact structure. First and second contact structures can be exposed at bonding and electrically interconnected as a result of the bonding. A via may be etched and filled after bonding to expose and form an electrical interconnect to interconnected first and second contact structures and provide electrical access to this interconnect from a surface. Alternatively, first and/or second contact structures are not exposed at bonding, and a via is etched and filled after bonding to electrically interconnect first and second contact structures and provide electrical access to interconnected first and second contact structure to a surface. Also, a device may be formed in a first substrate, the device being disposed in a device region of the first substrate and having a first contact structure. A via may be etched, or etched and filled, through the device region and into the first substrate before bonding and the first substrate thinned to expose the via, or filled via after bonding.

Abstract translation: 三维集成元件如单模或晶片的方法以及具有连接元件如单个模具或晶片的集成结构。 芯片和晶片中的任一个或两者可以具有形成在其中的半导体器件。 具有第一接触结构的第一元件被结合到具有第二接触结构的第二元件。 第一和第二接触结构可以在结合时暴露，并且由于接合而电连接。 可以在接合之后蚀刻和填充通孔，以暴露并形成互连的第一和第二接触结构的电互连并提供从表面到该互连的电接入。 或者，第一接触结构和/或第二接触结构在接合时不暴露，并且在接合之后蚀刻并填充通孔以将第一和第二接触结构电互连并且提供对互连的第一和第二接触结构到表面的电接触。 此外，器件可以形成在第一衬底中，该器件设置在第一衬底的器件区域中并且具有第一接触结构。 通孔可以在结合之前被蚀刻或蚀刻和填充穿过器件区域并进入第一衬底，并且第一衬底被稀释以暴露通孔，或者在结合之后填充通孔。

公开(公告)号：US20040235266A1

公开(公告)日：2004-11-25

申请号：US10440099

申请日：2003-05-19

Applicant: Ziptronix, Inc.

Inventor： Qin-Yi Tong

IPC: H01L021/30

CPC classification number: B32B7/04 ,  B32B2250/04 ,  B81C1/00357 ,  B81C2201/019 ,  B81C2203/0118 ,  B81C2203/019 ,  H01L21/3105 ,  H01L21/76251 ,  H01L24/26 ,  H01L24/29 ,  H01L24/81 ,  H01L24/83 ,  H01L24/92 ,  H01L2224/0401 ,  H01L2224/08059 ,  H01L2224/29186 ,  H01L2224/80896 ,  H01L2224/81894 ,  H01L2224/81895 ,  H01L2224/8319 ,  H01L2224/8385 ,  H01L2224/83894 ,  H01L2224/83896 ,  H01L2224/9202 ,  H01L2224/9212 ,  H01L2224/92125 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01016 ,  H01L2924/01018 ,  H01L2924/01019 ,  H01L2924/01023 ,  H01L2924/01033 ,  H01L2924/01039 ,  H01L2924/01058 ,  H01L2924/01067 ,  H01L2924/01072 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01082 ,  H01L2924/07802 ,  H01L2924/10253 ,  H01L2924/1305 ,  H01L2924/14 ,  H01L2924/1461 ,  H01L2924/351 ,  Y10T156/10 ,  Y10T428/24355 ,  Y10T428/24942 ,  Y10T428/31504 ,  Y10T428/31678 ,  H01L2924/3512 ,  H01L2924/00 ,  H01L2924/05442

Abstract: A method of bonding includes using a bonding layer having a fluorinated oxide. Fluorine may be introduced into the bonding layer by exposure to a fluorine-containing solution, vapor or gas or by implantation. The bonding layer may also be formed using a method where fluorine is introduced into the layer during its formation. The surface of the bonding layer is terminated with a desired species, preferably an NH2 species. This may be accomplished by exposing the bonding layer to an NH4OH solution. High bonding strength is obtained at room temperature. The method may also include bonding two bonding layers together and creating a fluorine distribution having a peak in the vicinity of the interface between the bonding layers. One of the bonding layers may include two oxide layers formed on each other. The fluorine concentration may also have a second peak at the interface between the two oxide layers.

Abstract translation: 接合方法包括使用具有氟化氧化物的接合层。 可以通过暴露于含氟溶液，蒸汽或气体或通过注入将氟引入结合层。 接合层也可以使用在其形成期间将氟引入层中的方法形成。 接合层的表面用所需的物质，优选NH 2物质终止。 这可以通过将结合层暴露于NH 4 OH溶液来实现。 在室温下获得高粘结强度。 该方法还可以包括将两个结合层结合在一起并产生在接合层之间的界面附近具有峰的氟分布。 结合层之一可以包括彼此形成的两个氧化物层。 氟浓度也可以在两个氧化物层之间的界面处具有第二个峰。