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    Interposer with programmable power gating granularity
    31.
    发明授权
    Interposer with programmable power gating granularity 有权
    内置可编程电源门控粒度

    公开(公告)号：US09059696B1

    公开(公告)日：2015-06-16

    申请号：US13957316

    申请日：2013-08-01

    Applicant: Altera Corporation

    Inventor： Arifur Rahman

    IPC: H03K19/173 ,  H03K19/00 ,  H03K19/0175 ,  H03K17/14

    CPC classification number: H03K19/0013 ,  H03K17/145 ,  H03K19/017581

    Abstract: A multichip package that includes an interposer and integrated circuits mounted on the interposer is provided. The interposer may include interposer routing circuitry and programmable power gating circuitry. At least one of the on-interposer integrated circuits may include power gating control logic that controls the programmable power gating circuitry. Circuitry on the integrated circuit may receive power supply voltage signals from the programmable power gating circuitry via the interposer routing circuitry. The programmable power gating circuitry may be configured to support fine, intermediate, and/or coarse power gating granularities. The programmable power gating circuitry may be used to selectively power down certain portions of the integrated circuit and may be used to provide desired power supply voltage levels to different voltage islands on the integrated circuit.

    Abstract translation: 提供了一种包括安装在插入器上的插入器和集成电路的多芯片封装。 插入器可以包括插入器路由电路和可编程电源选通电路。 至少一个插入式集成电路可以包括控制可编程电源门控电路的电源门控控制逻辑。 集成电路上的电路可以经由插入器路由电路从可编程电源门控电路接收电源电压信号。 可编程电源门控电路可以被配置为支持精细的，中间的和/或粗的电源门控粒度。 可编程电源门控电路可以用于选择性地将集成电路的某些部分断电，并且可以用于向集成电路上的不同电压岛提供期望的电源电压电平。

    Scalable 2.5D interface circuitry
    33.
    发明授权
    Scalable 2.5D interface circuitry 有权

    公开(公告)号：US11741042B2

    公开(公告)日：2023-08-29

    申请号：US17561917

    申请日：2021-12-24

    Applicant: Altera Corporation

    Inventor： Chee Hak Teh ,  Arifur Rahman

    IPC: G06F15/78 ,  G06F13/42 ,  G06F13/40 ,  G06F1/06 ,  G06F1/10

    CPC classification number: G06F15/7803 ,  G06F1/06 ,  G06F1/10 ,  G06F13/4022 ,  G06F13/4234 ,  G06F13/4291 ,  G06F15/7864 ,  Y02D10/00

    Abstract: A multichip package having a main die coupled to one or more daughter dies is provided. The main die may include embedded universal interface blocks (UIB) each of which can be used to interface with a corresponding daughter die to support high bandwidth parallel or serial communications. Each UIB may include an integrated processor subsystem and associated pattern sequencing logic to perform interface initialization and margining operations. Each UIB may perform simultaneous accesses to a daughter die across one or more channels. Each UIB may also include multiple phase-locked loop circuits for providing different clock signals to different portions of the UIB and a 2× clock phase generation logic. Each UIB may include multiple IO modules, each of which may optionally include its own duty cycle correction circuit. Each IO module may include buffer circuits, each of which may have a de-emphasis control logic for adjusting buffer drive strength.

    Scalable 2.5D interface circuitry
    35.
    发明授权
    Scalable 2.5D interface circuitry 有权

    公开(公告)号：US11157440B2

    公开(公告)日：2021-10-26

    申请号：US16833068

    申请日：2020-03-27

    Applicant: Altera Corporation

    Inventor： Chee Hak Teh ,  Arifur Rahman

    IPC: G06F13/00 ,  G06F13/40 ,  G06F15/78 ,  G06F13/42 ,  G06F1/06 ,  G06F1/10

    Abstract: A multichip package having a main die coupled to one or more daughter dies is provided. The main die may include embedded universal interface blocks (UIB) each of which can be used to interface with a corresponding daughter die to support high bandwidth parallel or serial communications. Each UIB may include an integrated processor subsystem and associated pattern sequencing logic to perform interface initialization and margining operations. Each UIB may perform simultaneous accesses to a daughter die across one or more channels. Each UIB may also include multiple phase-locked loop circuits for providing different clock signals to different portions of the UIB and a 2× clock phase generation logic. Each UIB may include multiple IO modules, each of which may optionally include its own duty cycle correction circuit. Each IO module may include buffer circuits, each of which may have a de-emphasis control logic for adjusting buffer drive strength.

    Programmable integrated circuits with in-operation reconfiguration capability
    36.
    发明授权
    Programmable integrated circuits with in-operation reconfiguration capability 有权

    公开(公告)号：US10591544B2

    公开(公告)日：2020-03-17

    申请号：US16043035

    申请日：2018-07-23

    Applicant: Altera Corporation

    Inventor： Dana How ,  Dinesh Patil ,  Arifur Rahman ,  Jeffrey Erik Schulz

    IPC: G06F11/20 ,  G06F11/16 ,  G01R31/3185 ,  G06F11/18 ,  G06F11/00 ,  G01R31/28 ,  H01L25/065

    Abstract: Integrated circuit packages with multiple integrated circuit dies are provided. A multichip package may include a master die that is coupled to one or more slave dies via inter-die package interconnects. A mixed (i.e., active and passive) interconnect redundancy scheme may be implemented to help repair potentially faulty interconnects to improve assembly yield. Interconnects that carry normal user signals may be repaired using an active redundancy scheme by selectively switching into use a spare driver block when necessary. On the other hand, interconnects that carry power-on-reset signals, initialization signals, and other critical control signals for synchronizing the operation between the master and slave dies may be supported using a passive redundancy scheme by using two or more duplicate wires for each critical signal.

    SCALABLE 2.5D INTERFACE CIRCUITRY
    37.
    发明申请
    SCALABLE 2.5D INTERFACE CIRCUITRY 审中-公开

    公开(公告)号：US20180239738A1

    公开(公告)日：2018-08-23

    申请号：US15954078

    申请日：2018-04-16

    Applicant: Altera Corporation

    Inventor： Chee Hak Teh ,  Arifur Rahman

    IPC: G06F15/78 ,  G06F1/08 ,  G06F13/40 ,  G06F13/42

    CPC classification number: G06F15/7803 ,  G06F1/06 ,  G06F1/10 ,  G06F13/4022 ,  G06F13/4234 ,  G06F13/4291 ,  G06F15/7864 ,  Y02D10/14 ,  Y02D10/151

    Abstract: A multichip package having a main die coupled to one or more daughter dies is provided. The main die may include embedded universal interface blocks (UIB) each of which can be used to interface with a corresponding daughter die to support high bandwidth parallel or serial communications. Each UIB may include an integrated processor subsystem and associated pattern sequencing logic to perform interface initialization and margining operations. Each UIB may perform simultaneous accesses to a daughter die across one or more channels. Each UIB may also include multiple phase-locked loop circuits for providing different clock signals to different portions of the UIB and a 2× clock phase generation logic. Each UIB may include multiple IO modules, each of which may optionally include its own duty cycle correction circuit. Each IO module may include buffer circuits, each of which may have a de-emphasis control logic for adjusting buffer drive strength.

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