公开(公告)号：US11740944B2

公开(公告)日：2023-08-29

申请号：US16711875

申请日：2019-12-12

Applicant: Advanced Micro Devices, Inc. ,  ATI Technologies ULC

Inventor： Amitabh Mehra ,  Anil Harwani ,  William Robert Alverson ,  Jerry Anton Ahrens, Jr. ,  Charles Sum Yuen Lee ,  John William Abshier

IPC: G06F1/324 ,  G06F9/50 ,  G06F9/4401 ,  G06F1/3287

CPC classification number: G06F9/5094 ,  G06F9/4403 ,  G06F1/324 ,  G06F1/3287

Abstract: A method and apparatus for managing processor functionality includes receiving, by the processor, data relating to one or more environmental conditions. The processor compares the data to pre-existing parameters to determine whether or not the environmental conditions are within the pre-existing parameters for normal operation. If the data are within the pre-existing parameters for normal operation, the processor is operated in a normal operation mode. If the data are outside the pre-existing parameters for normal operation, the processor operates in a second operation mode which is dynamically determined and calibrated during power-on, boot and operation.

公开(公告)号：US11675410B2

公开(公告)日：2023-06-13

申请号：US15949662

申请日：2018-04-10

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： Amitabh Mehra

IPC: G06F1/32 ,  G06F1/3206 ,  G06F1/324 ,  G06F1/329

CPC classification number: G06F1/3206 ,  G06F1/324 ,  G06F1/329

Abstract: A monitoring system predicts voltage droops at a processor by monitoring one or more performance characteristics of the processor, selecting a response policy based on the prediction, and adjusting a parameter of the processor. Multiple predictions of voltage droop conditions at different locations of the processor are made simultaneously, with the processor generating one or more responses and resulting in adjusting one or more parameters of the processor. By predicting voltage droop conditions before they occur, the deleterious effects of such droop conditions can be minimized or avoided.

公开(公告)号：US11579650B2

公开(公告)日：2023-02-14

申请号：US16721886

申请日：2019-12-19

Applicant: Advanced Micro Devices, Inc.

Inventor： Amitabh Mehra ,  David M. Dahle ,  Richard M. Born

IPC: G06F1/12

Abstract: A method and apparatus for synchronizing a time stamp counter (TSC) associated with a processor core in a computer system includes initializing the TSC associated with the processor core by synchronizing the TSC associated with the processor core with at least one other TSC in a hierarchy of TSCs. One or more processor cores are powered down. Upon powering up of the one or more processor cores, the TSC associated with the processor core is synchronized with the at least one other TSC in the hierarchy of TSCs.

公开(公告)号：US20210191454A1

公开(公告)日：2021-06-24

申请号：US16721886

申请日：2019-12-19

Applicant: Advanced Micro Devices, Inc.

Inventor： Amitabh Mehra ,  David M. Dahle ,  Richard M. Born

IPC: G06F1/12

Abstract: A method and apparatus for synchronizing a time stamp counter (TSC) associated with a processor core in a computer system includes initializing the TSC associated with the processor core by synchronizing the TSC associated with the processor core with at least one other TSC in a hierarchy of TSCs. One or more processor cores are powered down. Upon powering up of the one or more processor cores, the TSC associated with the processor core is synchronized with the at least one other TSC in the hierarchy of TSCs.

公开(公告)号：US20180018009A1

公开(公告)日：2018-01-18

申请号：US15208388

申请日：2016-07-12

Applicant: Advanced Micro Devices, Inc.

Inventor： Steven Kommrusch ,  Amitabh Mehra ,  Richard Martin Born ,  Bobby D. Young

IPC: G06F1/32

CPC classification number: G06F1/324 ,  G06F1/305 ,  Y02D10/126

Abstract: A processor adjusts frequencies of one or more clock signals in response to a voltage droop at the processor. The processor generates at least one clock signal by generating a plurality of base clock signals, each of the base clock signals having a common frequency but a different phase. The processor also generates a plurality of enable signals, wherein each enable signal governs whether a corresponding one of the base clock signals is used to generate the clock signal. The enable signals therefore determine the frequency of the clock signal. In response to detecting a voltage droop, the processor adjusts the enable signals used to generate the clock signal, thereby reducing the frequency of the clock signal droop.

公开(公告)号：US20250004514A1

公开(公告)日：2025-01-02

申请号：US18217390

申请日：2023-06-30

Applicant: Advanced Micro Devices, Inc ,  ATI Technologies ULC

Inventor： Amitabh Mehra ,  William Robert Alverson ,  Jerry Anton Ahrens ,  Grant Evan Ley ,  Joshua Taylor Knight ,  Anil Harwani ,  Adam Neil Calder Clark

IPC: G06F1/20 ,  G01K13/00

Abstract: Adjustable thermal management is described. Input to adjust one or more parameters for controlling thermal conditions of a component is received. Temperature measurements of a component are obtained from two or more sensors of the component. A temperature of a thermal hotspot of the component is estimated based on the temperature measurements obtained from the two or more sensors of the component and using the adjusted parameters. Operation of the component is adjusted based on the estimated temperature of the thermal hotspot.

公开(公告)号：US20240330134A1

公开(公告)日：2024-10-03

申请号：US18190664

申请日：2023-03-27

Applicant: Advanced Micro Devices, Inc.

Inventor： Jerry Anton Ahrens ,  William Robert Alverson ,  Joshua Taylor Knight ,  Amitabh Mehra ,  Anil Harwani ,  Grant Evan Ley

IPC: G06F11/22 ,  G06F9/4401

CPC classification number: G06F11/2284 ,  G06F9/4401

Abstract: A system that includes at least a system memory, a chipset link, and a chipset attached memory is powered down. A boot-up process is loaded in the chipset attached memory. The boot-up process is performed for the system, via the chipset link, by the chipset attached memory. The boot-up process includes loading one or more memory testing applications. The system memory is tested using the one or more memory testing applications loaded by the chipset attached memory.

公开(公告)号：US20240319712A1

公开(公告)日：2024-09-26

申请号：US18187848

申请日：2023-03-22

Applicant: Advanced Micro Devices, Inc ,  ATI Technologies ULC

Inventor： Jerry Anton Ahrens ,  Grant Evan Ley ,  Anil Harwani ,  Amitabh Mehra ,  Joshua Taylor Knight ,  William Robert Alverson ,  Adam Neil Calder Clark

IPC: G05B19/4155 ,  G01K7/01

CPC classification number: G05B19/4155 ,  G01K7/01 ,  G05B2219/49216

Abstract: Dynamic range aware conversion of sensor readings is described. A system includes one or more sensors to sense conditions of a component and output sensor readings and a system manager. The system manager is configured to convert the sensor readings into condition measurements by converting the sensor readings into the condition measurements using a first transformation while operating in a first conversion mode or converting the sensor readings into the condition measurements using a second transformation while operating in a second conversion mode. The system manager then adjusts operation of the component based on the condition measurements.

公开(公告)号：US20240220108A1

公开(公告)日：2024-07-04

申请号：US18147963

申请日：2022-12-29

Applicant: Advanced Micro Devices, Inc.

Inventor： Jayesh Hari Joshi ,  Alicia Wen Ju Yurie Leong ,  William Robert Alverson ,  Joshua Taylor Knight ,  Jerry Anton Ahrens ,  Grant Evan Ley ,  Amitabh Mehra ,  Anil Harwani

IPC: G06F3/06

CPC classification number: G06F3/061 ,  G06F3/0653 ,  G06F3/0673

Abstract: Automated memory overclocking is described. In accordance with the described techniques, one or more sets of overclocked memory settings of a memory are automatically selected for performance testing and stability testing of the memory. The one or more sets of the overclocked memory settings are tested for performance of the memory and a performance indication is output for each of the one or more sets of the overclocked memory settings. The one or more sets of the overclocked memory settings are tested for stability of the memory and a stability indication is output for each of the one or more sets of the overclocked memory settings. One of the one or more sets of the overclocked memory settings are selected as optimized overclocked memory settings for the memory.

公开(公告)号：US11977757B2

公开(公告)日：2024-05-07

申请号：US17732718

申请日：2022-04-29

Applicant: Advanced Micro Devices, Inc.

Inventor： Grant Evan Ley ,  Jayesh Hari Joshi ,  Amitabh Mehra ,  Jerry Anton Ahrens ,  Joshua Taylor Knight ,  Anil Harwani ,  William Robert Alverson

IPC: G06F3/06

CPC classification number: G06F3/0634 ,  G06F3/0604 ,  G06F3/0613 ,  G06F3/0673

Abstract: Profile switching for memory overclocking is described. In accordance with the described techniques, a memory is operated according to a first memory profile. During operation of the memory according to the first memory profile, a request is received to operate the memory according to a second memory profile. Responsive to the request, operation of the memory is switched to operate according to the second memory profile without rebooting. In one or more implementations, at least one of the first memory profile or the second memory profile comprises an overclocking memory profile that configures the memory to operate in an overclocking mode. In one or more implementations, the memory is trained to operate according to the overclocking memory profile prior to operating the memory according to the first memory profile.