公开(公告)号：US11515270B2

公开(公告)日：2022-11-29

申请号：US17067561

申请日：2020-10-09

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Yu-Lin Shih ,  Chih-Cheng Lee

IPC: H01L23/66 ,  H01L23/49 ,  H01L23/538 ,  H01L21/683 ,  H01L21/48 ,  H01L21/56 ,  H01Q1/22 ,  H01Q1/40 ,  H01L23/31

Abstract: An antenna package includes a conductive layer, an interconnection structure and an antenna. The interconnection structure is disposed on the conductive layer. The interconnection structure includes a conductive via and a first package body. The conductive via has a first surface facing the conductive layer, a second surface opposite to the first surface and a lateral surface extending from the first surface to the second surface. The first package body covers the lateral surface of the conductive via and exposes the first surface and the second surface of the conductive via. The first package body is spaced apart from the conductive layer. The antenna is electrically connected to the second surface of the conductive via.

公开(公告)号：US11205628B2

公开(公告)日：2021-12-21

申请号：US16730390

申请日：2019-12-30

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Yu-Lin Shih ,  Chih-Cheng Lee

IPC: H01L23/00 ,  H01L21/768 ,  H01L23/528

Abstract: A semiconductor device package and a method of manufacturing the same are provided. The semiconductor device package includes a circuit structure. The circuit structure includes a dielectric layer and a bonding pad. The dielectric layer has a first dielectric surface and a second dielectric surface opposite to the first dielectric surface, where the dielectric layer defines a recess in the first dielectric surface, and the recess includes a sidewall. The bonding pad is disposed in the recess, where a first pad surface of the bonding pad is adjacent to the first dielectric surface, a second pad surface of the bonding pad is adjacent to the second dielectric surface, and an edge of the bonding pad is spaced from the sidewall of the recess by a first distance.

公开(公告)号：US10665523B2

公开(公告)日：2020-05-26

申请号：US16038037

申请日：2018-07-17

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Cheng-Lin Ho ,  Chih-Cheng Lee

IPC: H01L23/00 ,  H01L23/367 ,  H01L21/768 ,  H01L23/373

Abstract: The present disclosure provides a semiconductor substrate, including a first patterned conductive layer, a dielectric structure on the first patterned conductive layer, wherein the dielectric structure having a side surface, a second patterned conductive layer on the dielectric structure and extending on the side surface, and a third patterned conductive layer on the second patterned conductive layer and extending on the side surface. The present disclosure provides a semiconductor package including the semiconductor substrate. A method for manufacturing the semiconductor substrate and the semiconductor package is also provided.

公开(公告)号：US10446515B2

公开(公告)日：2019-10-15

申请号：US15450598

申请日：2017-03-06

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Li Chuan Tsai ,  Chih-Cheng Lee

IPC: H01L23/498 ,  H01L23/00 ,  H01L21/48

Abstract: A semiconductor substrate includes a first dielectric layer, a first patterned conductive layer disposed in the first dielectric layer, a second dielectric layer disposed on the first dielectric layer, and a first bump pad disposed in the second dielectric layer. The first bump pad is electrically connected to the first patterned conductive layer, and the first bump pad has a curved surface surrounded by the second dielectric layer.

公开(公告)号：US10325842B2

公开(公告)日：2019-06-18

申请号：US15699816

申请日：2017-09-08

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Chih-Cheng Lee ,  Yuan-Chang Su

IPC: H05K1/02 ,  H01L23/498 ,  H01L21/48 ,  H01L21/683

Abstract: A substrate for packaging a semiconductor device includes a first dielectric layer having a first surface and a second surface opposite to the first surface, a first patterned conductive layer adjacent to the first surface of the first dielectric layer, and a second patterned conductive layer adjacent to the second surface of the first dielectric layer and electrically connected to the first patterned conductive layer. The first patterned conductive layer includes a first portion and a second portion. Each of the first portion and the second portion is embedded in the first dielectric layer and protrudes relative to the first surface of the first dielectric layer toward a direction away from the second surface of the first dielectric layer. A thickness of the first portion of the first patterned conductive layer is greater than a thickness of the second portion of the first patterned conductive layer.

公开(公告)号：US20190148280A1

公开(公告)日：2019-05-16

申请号：US16247441

申请日：2019-01-14

Applicant: ADVANCED SEMICONDUCTOR ENGINEERING, INC.

Inventor： Chun-Che Lee ,  Ming-Chiang Lee ,  Yuan-Chang Su ,  Tien-Szu Chen ,  Chih-Cheng Lee ,  You-Lung Yen

IPC: H01L23/498 ,  H01L21/48 ,  H05K1/11 ,  H05K3/00

Abstract: A semiconductor substrate and a manufacturing method thereof are provided. The semiconductor substrate includes a dielectric layer, a circuit layer, a first protection layer and a plurality of conductive posts. The dielectric layer has a first surface and a second surface that are opposite to each other. The circuit layer is embedded in the dielectric layer and is exposed from the first surface. The first protection layer covers a portion of the first circuit layer and defines a plurality of holes that expose a remaining portion of the first circuit layer. The conductive posts are formed in the holes.

公开(公告)号：US10128198B2

公开(公告)日：2018-11-13

申请号：US15495282

申请日：2017-04-24

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： You-Lung Yen ,  Chih-Cheng Lee ,  Yuan-Chang Su

IPC: H01L23/00 ,  H01L23/498 ,  H01L23/31 ,  H01L21/48

Abstract: An interposer substrate includes a first circuit pattern embedded at a first surface of a dielectric layer and a second circuit pattern embedded at a second surface of the dielectric layer; a middle patterned conductive layer in the dielectric layer between the first circuit pattern and the second circuit pattern; first conductive vias, where each first conductive via includes a first end adjacent to the first circuit pattern and a second end adjacent to the middle patterned conductive layer, wherein a width of the first end is greater than a width of the second end; second conductive vias, where each second conductive via including a third end adjacent to the second circuit pattern and a fourth end adjacent to the middle patterned conductive layer, wherein a width of the third end is greater than a width of the fourth end.

公开(公告)号：US10079156B2

公开(公告)日：2018-09-18

申请号：US14703794

申请日：2015-05-04

Applicant: ADVANCED SEMICONDUCTOR ENGINEERING, INC.

Inventor： Chih-Cheng Lee ,  Yuan-Chang Su ,  Yu-Lin Shih ,  You-Lung Yen

IPC: H01L21/48 ,  H01L23/31 ,  H01L23/00 ,  H01L23/498 ,  H01L23/538 ,  H01L21/56

CPC classification number: H01L21/481 ,  H01L21/568 ,  H01L23/3121 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/20 ,  H01L2224/04105 ,  H01L2224/92144

Abstract: The present disclosure relates to a semiconductor package and method of making the same. The semiconductor package includes an encapsulation layer, a component within the encapsulation layer, a first dielectric layer, a second dielectric layer, a first patterned conductive layer, and a second patterned conductive layer. The component includes pads on a front surface of the component. The first dielectric layer is disposed on a surface of the encapsulation layer. The second dielectric layer is disposed on a surface of the first dielectric layer. The first and second dielectric layers define via holes extending from the second dielectric layer to respective ones of the pads. The first patterned conductive layer is disposed within the first dielectric layer and surrounds the via holes. The second patterned conductive layer is disposed within the second dielectric layer and surrounds the via holes.

公开(公告)号：US09997442B1

公开(公告)日：2018-06-12

申请号：US15379362

申请日：2016-12-14

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Chai-Chi Lin ,  Chih-Cheng Lee ,  Hsing Kuo Tien ,  Chih-Yung Yang

IPC: H01L23/498 ,  H01L23/538 ,  H01L21/48 ,  H01L25/18 ,  H01L25/16 ,  H01L25/065

CPC classification number: H01L23/49822 ,  H01L21/481 ,  H01L21/4857 ,  H01L21/486 ,  H01L23/49827 ,  H01L23/49838 ,  H01L23/5383 ,  H01L23/5384 ,  H01L23/5386 ,  H01L25/0655 ,  H01L25/16 ,  H01L25/18 ,  H01L2224/16225

Abstract: A semiconductor substrate includes an interconnection structure and a dielectric layer. The dielectric layer surrounds the interconnection structure and defines a first cavity. The first cavity is defined by a first sidewall, a second sidewall, and a first surface of the dielectric layer. The first sidewall is laterally displaced from the second sidewall.

公开(公告)号：US09966333B2

公开(公告)日：2018-05-08

申请号：US15725144

申请日：2017-10-04

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Li-Chuan Tsai ,  Chih-Cheng Lee

IPC: H05K1/11 ,  H05K1/16 ,  H05K1/09 ,  H05K1/03 ,  H05K7/00 ,  H05K1/18 ,  H01L23/498 ,  H05K1/02 ,  H01L21/48 ,  H05K3/00 ,  H05K3/22 ,  H05K3/36 ,  H05K3/40 ,  H01L23/00

CPC classification number: H01L23/49838 ,  H01L21/4857 ,  H01L21/486 ,  H01L23/49822 ,  H01L23/49827 ,  H01L24/17 ,  H01L2224/16227 ,  H01L2924/15153 ,  H01L2924/15313 ,  H01L2924/19105 ,  H05K1/0266 ,  H05K1/0298 ,  H05K1/111 ,  H05K1/115 ,  H05K1/181 ,  H05K1/183 ,  H05K3/0017 ,  H05K3/0026 ,  H05K3/0047 ,  H05K3/22 ,  H05K3/36 ,  H05K3/40 ,  H05K3/4682 ,  H05K3/4697 ,  H05K2201/0158 ,  H05K2201/09472 ,  H05K2201/09527 ,  H05K2201/10204 ,  H05K2203/166 ,  Y02P70/611

Abstract: A semiconductor substrate includes: (1) a first dielectric structure having a first surface and a second surface opposite the first surface; (2) a second dielectric structure having a third surface and a fourth surface opposite the third surface, wherein the fourth surface faces the first surface, the second dielectric structure defining a through hole extending from the third surface to the fourth surface, wherein a cavity is defined by the through hole and the first dielectric structure; (3) a first patterned conductive layer, disposed on the first surface of the first dielectric structure; and (4) a second patterned conductive layer, disposed on and contacting the second surface of the first dielectric structure and including at least one conductive trace, wherein the first dielectric structure defines at least one opening, and a periphery of the opening corresponds to a periphery of the through hole of the second dielectric structure.