公开(公告)号：US20210193468A1

公开(公告)日：2021-06-24

申请号：US17192213

申请日：2021-03-04

Applicant: Applied Materials, Inc.

Inventor： Steven C.H. Hung ,  Lin Dong ,  Benjamin Colombeau ,  Johanes F. Swenberg ,  Linlin Wang

IPC: H01L21/28 ,  H01L29/51 ,  H01L21/02

Abstract: A method of forming a semiconductor structure includes annealing a surface of a substrate in an ambient of hydrogen to smooth the surface, pre-cleaning the surface of the substrate, depositing a high-κ dielectric layer on the pre-cleaned surface of the substrate, performing a re-oxidation process to thermally oxidize the surface of the substrate; performing a plasma nitridation process to insert nitrogen atoms in the deposited high-κ dielectric layer, and performing a post-nitridation anneal process to passivate chemical bonds in the plasma nitridated high-κ dielectric layer.

公开(公告)号：US20210104617A1

公开(公告)日：2021-04-08

申请号：US17037941

申请日：2020-09-30

Applicant: Applied Materials, Inc.

Inventor： Steven C.H. Hung ,  Benjamin Colombeau ,  Andy Lo ,  Byeong Chan Lee ,  Johanes F. Swenberg ,  Theresa Kramer Guarini ,  Malcolm J. Bevan

IPC: H01L29/66 ,  C30B29/06 ,  C30B29/52 ,  C23C8/02 ,  C23C8/16 ,  C23C8/80 ,  C23C16/455 ,  C23C16/56

Abstract: Described is a method of manufacturing a gate-all-around electronic device. The method includes forming a thermal oxide layer though an enhanced in situ steam generation process in combination with atomic layer deposition of a low-κ layer. The thin thermal oxide layer passivates the interface between the silicon layer and the dielectric layer of the GAA. A passivation process after the deposition of the low-κ layer reduces the bulk trap and enhances the breakdown performance of the GAA transistor.

公开(公告)号：US10573719B2

公开(公告)日：2020-02-25

申请号：US15279257

申请日：2016-09-28

Applicant: Applied Materials, Inc.

Inventor： Shiyu Sun ,  Naomi Yoshida ,  Theresa Kramer Guarini ,  Sung Won Jun ,  Benjamin Colombeau ,  Michael Chudzik

IPC: H01L21/76 ,  H01L29/423 ,  H01L21/02 ,  H01L21/306 ,  H01L21/762 ,  H01L29/66 ,  H01L29/786 ,  H01L29/15

Abstract: Embodiments described herein generally relate to methods and apparatus for horizontal gate all around (hGAA) isolation. A superlattice structure comprising different materials arranged in an alternatingly stacked formation may be formed on a substrate. The different materials may be silicon containing materials and one or more III/V materials. In one embodiment, at least one of the layers of the superlattice structure may be oxidized to form a buried oxide layer adjacent the substrate.

公开(公告)号：US09460920B1

公开(公告)日：2016-10-04

申请号：US14755099

申请日：2015-06-30

Applicant: Applied Materials, Inc.

Inventor： Shiyu Sun ,  Naomi Yoshida ,  Theresa Kramer Guarini ,  Sung Won Jun ,  Benjamin Colombeau ,  Michael Chudzik

IPC: H01L21/76 ,  H01L21/02 ,  H01L21/762 ,  H01L29/66

CPC classification number: H01L29/66795 ,  H01L29/42392 ,  H01L29/66742

Abstract: Embodiments described herein generally relate to methods and apparatus for horizontal gate all around (hGAA) isolation. A superlattice structure comprising different materials arranged in an alternatingly stacked formation may be formed on a substrate. The different materials may be silicon containing materials and one or more III/V materials. In one embodiment, at least one of the layers of the superlattice structure may be oxidized to form a buried oxide layer adjacent the substrate.

Abstract translation: 本文描述的实施例通常涉及用于水平门全周（hGAA）隔离的方法和装置。 可以在衬底上形成包括布置在交替堆叠的层中的不同材料的超晶格结构。 不同的材料可以是含硅材料和一种或多种III / V材料。 在一个实施例中，超晶格结构的至少一个层可以被氧化以形成邻近衬底的掩埋氧化物层。

公开(公告)号：US12243941B2

公开(公告)日：2025-03-04

申请号：US17386711

申请日：2021-07-28

Applicant: Applied Materials, Inc.

Inventor： Myungsun Kim ,  Michael Stolfi ,  Benjamin Colombeau ,  Andy Lo

IPC: H01L29/78 ,  H01L21/02 ,  H01L21/8234 ,  H01L29/06 ,  H01L29/15 ,  H01L29/16 ,  H01L29/423 ,  H01L29/786 ,  H01L29/66

Abstract: Horizontal gate-all-around devices and methods of manufacturing the same are described. The hGAA devices comprise an oxidize layer on a semiconductor material between source regions and drain regions of the device. The method includes radical plasma oxidation (RPO) of semiconductor material layers between source regions and drain regions of an electronic device.

公开(公告)号：US12183798B2

公开(公告)日：2024-12-31

申请号：US17528863

申请日：2021-11-17

Applicant: Applied Materials, Inc.

Inventor： Steven C. H. Hung ,  Benjamin Colombeau ,  Myungsun Kim ,  Srinivas Gandikota ,  Yixiong Yang ,  Jacqueline Samantha Wrench ,  Yong Yang

IPC: H01L29/423 ,  H01L29/06 ,  H01L29/78 ,  H01L29/786

Abstract: A method of forming a gate stack structure includes forming a dipole metal layer on a high-κ gate dielectric layer on a semiconductor structure formed on a substrate, annealing the dipole metal layer, and removing the dipole metal layer. The dipole metal layer comprises dopants in the high-κ gate dielectric layer.

公开(公告)号：US20240321584A1

公开(公告)日：2024-09-26

申请号：US18603360

申请日：2024-03-13

Applicant: Applied Materials, Inc.

Inventor： Byeong Chan Lee ,  Benjamin Colombeau ,  Edy Cardona ,  Christopher S. Olsen ,  Shawn Thomas

IPC: H01L21/3065 ,  H01L21/02 ,  H01L29/66

CPC classification number: H01L21/3065 ,  H01L21/02057 ,  H01L21/02236 ,  H01L21/02532 ,  H01L29/66439

Abstract: Semiconductor devices, such as gate-all-around (GAA) devices, and methods of forming semiconductor devices are described. Selective oxidation processes that are useful in front-end of line (FEOL) and back-end of line (BEOL) applications and processes are also described. In FEOL processes, for example, selective oxidation protects silicon germanium (SiGe) layers during etching silicon (Si) channel recess when there is no dielectric inner spacer present. In BEOL processes, for example, selective oxidation protects growth of silicon germanium (SiGe) layers on the sidewall of a superlattice structure during bottom-up epitaxial growth.

公开(公告)号：US20240290885A1

公开(公告)日：2024-08-29

申请号：US18441886

申请日：2024-02-14

Applicant: Applied Materials, Inc.

Inventor： Sai Hooi Yeong ,  Benjamin Colombeau ,  Balasubramanian Pranatharthiharan ,  El Mehdi Bazizi ,  Hui Zhao ,  Ashish Pal

IPC: H01L29/78 ,  H01L21/762 ,  H01L21/768 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66 ,  H01L29/775 ,  H01L29/786

CPC classification number: H01L29/7846 ,  H01L21/76224 ,  H01L21/76831 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/775 ,  H01L29/78696

Abstract: The present technology includes semiconductor devices with improved stress in a channel region. The semiconductor device includes a substrate, a source region, a drain region, a channel region that includes at least one channel located between the source and the drain. Devices include a first gate region having a first self-aligned single diffusion break in a n-MOS region, and a second gate region includes having a self-aligned single diffusion break in a p-MOS region. The second self-aligned single diffusion break also contains a liner and a compressive stressed material, where the stressed metal fill exhibits a compressive stress of about 350 MPa or greater.

公开(公告)号：US20240038553A1

公开(公告)日：2024-02-01

申请号：US18225799

申请日：2023-07-25

Applicant: Applied Materials, Inc.

Inventor： Benjamin Colombeau ,  Balasubramanian Pranatharthiharan ,  Lequn Liu ,  Brian K. Kirkpatrick

IPC: H01L21/67 ,  H01L29/66

CPC classification number: H01L21/67069 ,  H01L29/66545 ,  H01L21/67075 ,  H01L21/67167 ,  H01L21/67207 ,  H01L29/66439 ,  H01L29/0673

Abstract: Semiconductor devices (e.g., GAA device structures) and processing methods and cluster tools for forming GAA device structures are described. The cluster tools for forming GAA device structures comprise a first etch chamber, a second etch chamber, and a third etch chamber. Each of the first etch chamber and the second etch chamber independently comprises a single-wafer chamber or an immersion chamber. One or more of the first etch chamber or the second etch chamber may be a wet etch chamber. In some embodiments, at least one of the first etch chamber, the second etch chamber, and the third etch chamber is a dry etch chamber. The cluster tool described herein advantageously reduces the number of cleaning processes, the total time between cleaning and processing operations, variations in time between processing and variation in sidewall loss compared to conventional cluster tools.

公开(公告)号：US20240014214A1

公开(公告)日：2024-01-11

申请号：US18219993

申请日：2023-07-10

Applicant: Applied Materials, Inc.

Inventor： Sai Hooi Yeong ,  Jody A. Fronheiser ,  Benjamin Colombeau ,  Balasubramanian Pranatharthiharan ,  El Mehdi Bazizi ,  Ashish Pal

IPC: H01L27/092 ,  H01L29/66 ,  H01L29/423 ,  H01L29/786 ,  H01L29/775 ,  H01L29/15 ,  H01L21/8238 ,  H01L29/06

CPC classification number: H01L27/0924 ,  H01L29/66545 ,  H01L29/42392 ,  H01L29/78696 ,  H01L29/775 ,  H01L29/15 ,  H01L29/66439 ,  H01L21/823807 ,  H01L29/0673

Abstract: Horizontal gate-all-around devices and methods of manufacturing same are described. The hGAA devices comprise a semiconductor material between source regions and drain regions of the device. The method includes formation of a cladding material on a first material followed by a dry oxidation process resulting rearrangement of the cladding material and first material.