公开(公告)号：US20200168709A1

公开(公告)日：2020-05-28

申请号：US16694070

申请日：2019-11-25

Applicant: Infineon Technologies AG

Inventor： Albert Birner ,  Jan Ropohl

IPC: H01L29/20 ,  H01L29/45 ,  H01L21/283 ,  H01L29/40

Abstract: In an embodiment, a Group III nitride device includes a multilayer Group III nitride structure and a first ohmic contact arranged on and forming an ohmic contact to the multilayer Group III nitride device structure. The first ohmic contact includes a base portion having a conductive surface, the conductive surface including a peripheral portion and a central portion, the peripheral portion and the central portion being substantially coplanar and being of differing composition, a conductive via positioned on the central portion of the conductive surface and a contact pad positioned on the conductive via.

公开(公告)号：US10304789B2

公开(公告)日：2019-05-28

申请号：US15986433

申请日：2018-05-22

Applicant: Infineon Technologies AG

Inventor： Helmut Brech ,  Albert Birner ,  Matthias Zigldrum ,  Michaela Braun ,  Jan Ropohl

IPC: H01L23/48 ,  H01L21/768 ,  H01L23/66 ,  H01L49/02 ,  H01L29/78 ,  H03F3/193 ,  H03F3/21 ,  H01L23/522

Abstract: In an embodiment, a method includes forming a first opening in a front surface of a semiconductor substrate including a LDMOS transistor structure, and covering the first opening with a first layer to form an enclosed cavity defined by material of the semiconductor substrate and the first layer. The material of the first layer lines sidewalls of the enclosed cavity.

公开(公告)号：US20180374921A1

公开(公告)日：2018-12-27

申请号：US16120855

申请日：2018-09-04

Applicant: Infineon Technologies AG

Inventor： Albert Birner ,  Helmut Brech ,  Simone Lavanga

IPC: H01L29/205 ,  H01L21/3105 ,  H01L21/02 ,  H01L21/304 ,  H01L21/762 ,  H01L29/20 ,  H01L29/10 ,  H01L29/66 ,  H01L29/778

CPC classification number: H01L29/205 ,  H01L21/02378 ,  H01L21/02381 ,  H01L21/02433 ,  H01L21/0254 ,  H01L21/304 ,  H01L21/31053 ,  H01L21/31056 ,  H01L21/76229 ,  H01L29/1066 ,  H01L29/2003 ,  H01L29/66462 ,  H01L29/778 ,  H01L29/7786

Abstract: In an embodiment, a semiconductor wafer includes a substrate wafer having a device surface region surrounded by a peripheral region, one or more mesas including a Group III nitride layer arranged on the device surface region, and an oxide layer arranged on the device surface region and on the peripheral region. The oxide layer has an upper surface that is substantially coplanar with an upper surface of the one or more mesas.

公开(公告)号：US10020270B2

公开(公告)日：2018-07-10

申请号：US15279649

申请日：2016-09-29

Applicant: Infineon Technologies AG

Inventor： Helmut Brech ,  Albert Birner ,  Matthias Zigldrum ,  Michaela Braun ,  Jan Ropohl

IPC: H01L23/66 ,  H01L29/78 ,  H01L23/48 ,  H01L49/02 ,  H01L21/768 ,  H03F3/193 ,  H03F3/21

CPC classification number: H01L23/66 ,  H01L21/7682 ,  H01L21/76898 ,  H01L23/481 ,  H01L23/522 ,  H01L28/10 ,  H01L28/20 ,  H01L28/40 ,  H01L29/1083 ,  H01L29/1095 ,  H01L29/404 ,  H01L29/7816 ,  H01L29/7835 ,  H01L2223/6616 ,  H01L2223/6644 ,  H01L2223/6655 ,  H01L2223/6683 ,  H03F3/193 ,  H03F3/21 ,  H03F2200/222 ,  H03F2200/411

Abstract: In an embodiment, a semiconductor device includes a semiconductor substrate including a front surface, an LDMOS transistor structure in the front surface, a conductive interconnection structure arranged on the front surface, and at least one cavity arranged in the front surface.

公开(公告)号：US10014230B2

公开(公告)日：2018-07-03

申请号：US15352392

申请日：2016-11-15

Applicant: Infineon Technologies AG

Inventor： Albert Birner ,  Tobias Herzig

IPC: H01L21/00 ,  H01L21/66 ,  H01L21/768 ,  H01L23/48 ,  H01L23/31

CPC classification number: H01L22/26 ,  H01L21/76898 ,  H01L22/12 ,  H01L22/20 ,  H01L22/30 ,  H01L22/32 ,  H01L23/3107 ,  H01L23/481 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method of forming an electronic device includes forming a first opening and a second opening in a workpiece. The first opening is deeper than the second opening. The method further includes forming a fill material within the first opening to form part of a through via and forming the fill material within the second opening.

公开(公告)号：US20180138086A1

公开(公告)日：2018-05-17

申请号：US15856742

申请日：2017-12-28

Applicant: Infineon Technologies AG

Inventor： Albert Birner ,  Tobias Herzig

IPC: H01L21/768 ,  H01L23/532 ,  H01L23/528 ,  H01L23/522 ,  H01L21/288 ,  H01L23/48

Abstract: In an embodiment, a substrate includes semiconductor material and a conductive via. The conductive via includes a via in the substrate, a conductive plug filling a first portion of the via, and a conductive liner layer that lines side walls of a second portion of the via and is electrically coupled to the conductive plug. The conductive liner layer and the conductive plug have different microstructures.

公开(公告)号：US09634085B1

公开(公告)日：2017-04-25

申请号：US15191854

申请日：2016-06-24

Applicant: Infineon Technologies AG

Inventor： Albert Birner ,  Helmut Brech ,  Matthias Zigldrum ,  Michaela Braun ,  Christian Eckl

IPC: H01L29/66 ,  H01L29/06 ,  H01L29/78 ,  H01L29/10 ,  H01L21/265 ,  H01L21/768 ,  H01L23/528

Abstract: In an embodiment, a semiconductor device includes a semiconductor substrate having a bulk resistivity ρ≧100 Ohm·cm, a front surface and a rear surface, at least one LDMOS transistor in the semiconductor substrate, and a RESURF structure. The RESURF structure includes a doped buried layer arranged in the semiconductor substrate, spaced at a distance from the front surface and the rear surface, and coupled with at least one of a channel region and a body contact region of the LDMOS transistor.

公开(公告)号：US20150243649A1

公开(公告)日：2015-08-27

申请号：US14186840

申请日：2014-02-21

Applicant: Infineon Technologies AG

Inventor： Helmut Brech ,  Matthias Zigldrum ,  Albert Birner ,  Richard Wilson ,  Saurabh Goel

IPC: H01L27/06 ,  H01L23/00 ,  H01L23/528 ,  H01L23/522 ,  H01L49/02

CPC classification number: H01L27/0629 ,  H01L23/4824 ,  H01L23/5223 ,  H01L23/5226 ,  H01L23/528 ,  H01L24/05 ,  H01L24/09 ,  H01L28/40 ,  H01L29/7802 ,  H01L29/7816 ,  H01L2223/6655 ,  H01L2223/6672 ,  H01L2224/04042 ,  H01L2224/0603 ,  H01L2224/0616 ,  H01L2224/0912 ,  H01L2224/48195 ,  H01L2224/48247 ,  H01L2224/49111 ,  H01L2224/49175 ,  H01L2924/1205 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/13063 ,  H01L2924/13064 ,  H01L2924/13091 ,  H01L2924/1421 ,  H01L2924/19041 ,  H01L2924/19105 ,  H01L2924/19107 ,  H01L2924/30105 ,  H01L2924/00 ,  H01L2924/0001

Abstract: A power transistor die includes a transistor formed in a semiconductor body. The transistor has a gate terminal, an output terminal and a third terminal. The gate terminal controls a conduction channel between the output terminal and the third terminal. The power transistor die further includes a structured first metal layer disposed on and insulated from the semiconductor body. The structured first metal layer is connected to the output terminal of the transistor. The power transistor die also includes a first bond pad disposed on and insulated from the semiconductor body. The first bond pad forms an output terminal of the power transistor die and is capacitively coupled to the structured first metal layer so as to form a series capacitance between the output terminal of the transistor and the first bond pad. A power semiconductor package including the power transistor die is also provided.

Abstract translation: 功率晶体管管芯包括形成在半导体本体中的晶体管。 晶体管具有栅极端子，输出端子和第三端子。 栅极端子控制输出端子和第三端子之间的导通通道。 功率晶体管管芯还包括设置在半导体本体上并与半导体本体绝缘的结构化的第一金属层。 结构化的第一金属层连接到晶体管的输出端。 功率晶体管管芯还包括设置在半导体本体上并与半导体本体绝缘的第一接合焊盘。 第一接合焊盘形成功率晶体管管芯的输出端子，并且与结构化的第一金属层电容耦合，以便在晶体管的输出端和第一接合焊盘之间形成串联电容。 还提供了包括功率晶体管管芯的功率半导体封装。

公开(公告)号：US12087830B2

公开(公告)日：2024-09-10

申请号：US17237178

申请日：2021-04-22

Applicant: Infineon Technologies AG

Inventor： Albert Birner ,  Helmut Brech ,  John Twynam

IPC: H01L29/40 ,  H01L21/765 ,  H01L23/29 ,  H01L23/31 ,  H01L29/20 ,  H01L29/205 ,  H01L29/66 ,  H01L29/778

CPC classification number: H01L29/402 ,  H01L21/765 ,  H01L23/291 ,  H01L23/3171 ,  H01L29/2003 ,  H01L29/205 ,  H01L29/401 ,  H01L29/66462 ,  H01L29/7786

Abstract: In an embodiment, a Group III nitride-based transistor device includes a first passivation layer arranged on a first major surface of a Group III nitride-based layer, a second passivation layer arranged on the first passivation layer, a source ohmic contact, a drain ohmic contact and a gate positioned on the first major surface of a Group III nitride-based layer, and a field plate, the field plate being laterally arranged between and spaced apart from the gate and the drain ohmic contact.

公开(公告)号：US11728389B2

公开(公告)日：2023-08-15

申请号：US17695366

申请日：2022-03-15

Applicant: Infineon Technologies AG

Inventor： Albert Birner ,  Jan Ropohl

IPC: H01L29/45 ,  H01L29/20 ,  H01L21/283 ,  H01L29/40 ,  H01L29/778

CPC classification number: H01L29/2003 ,  H01L21/283 ,  H01L29/401 ,  H01L29/452 ,  H01L29/778

Abstract: In an embodiment, a Group III nitride device includes a multilayer Group III nitride structure and a first ohmic contact arranged on and forming an ohmic contact to the multilayer Group III nitride device structure. The first ohmic contact includes a base portion having a conductive surface, the conductive surface including a peripheral portion and a central portion, the peripheral portion and the central portion being substantially coplanar and being of differing composition, a conductive via positioned on the central portion of the conductive surface and a contact pad positioned on the conductive via.