公开(公告)号：US11374056B2

公开(公告)日：2022-06-28

申请号：US16630924

申请日：2017-09-14

Applicant: Intel Corporation

Inventor： Elijah V. Karpov ,  Brian S. Doyle ,  Ravi Pillarisetty ,  Prashant Majhi ,  Abhishek A. Sharma

IPC: H01L27/24 ,  H01L27/22 ,  H01L45/00

Abstract: Disclosed herein are selector devices and related devices and techniques. In some embodiments, a selector device may include a first electrode, a second electrode, and a selector material between the first electrode and the second electrode. The selector material may include germanium, tellurium, and sulfur.

公开(公告)号：US20220181256A1

公开(公告)日：2022-06-09

申请号：US17114537

申请日：2020-12-08

Applicant: Intel Corporation

Inventor： Wilfred Gomes ,  Abhishek A. Sharma ,  Mauro J. Kobrinsky ,  Doug B. Ingerly

IPC: H01L23/528 ,  H01L23/00 ,  H01L23/522 ,  H01L25/18 ,  H01L23/48

Abstract: Microelectronic assemblies fabricated using hybrid manufacturing, as well as related devices and methods, are disclosed herein. As used herein, “hybrid manufacturing” refers to fabricating a microelectronic assembly by arranging together at least two IC structures fabricated by different manufacturers, using different materials, or different manufacturing techniques. For example, a microelectronic assembly may include a first IC structure that includes first interconnects and a second IC structure that includes second interconnects, where at least some of the first and second interconnects may include a liner and an electrically conductive fill material, and where a material composition of the liner/electrically conductive fill material of the first interconnects may be different from a material composition of the liner/electrically conductive fill material of the second interconnects.

公开(公告)号：US11309400B2

公开(公告)日：2022-04-19

申请号：US16650153

申请日：2018-01-12

Applicant: INTEL CORPORATION

Inventor： Seung Hoon Sung ,  Abhishek A. Sharma ,  Van H. Le ,  Gilbert Dewey ,  Jack T. Kavalieros ,  Tahir Ghani

IPC: H01L29/66 ,  H01L29/417 ,  H01L29/423 ,  H01L27/12 ,  H01L29/786 ,  H01L29/06

Abstract: Thin film transistor structures and processes are disclosed that include stacked nanowire bodies to mitigate undesirable short channel effects, which can occur as gate lengths scale down to sub-100 nanometer (nm) dimensions, and to reduce external contact resistance. In an example embodiment, the disclosed structures employ a gate-all-around architecture, in which the gate stack (including a high-k dielectric layer) wraps around each of the stacked channel region nanowires (or nanoribbons) to provide improved electrostatic control. The resulting increased gate surface contact area also provides improved conduction. Additionally, these thin film structures can be stacked with relatively small spacing (e.g., 1 to 20 nm) between nanowire bodies to increase integrated circuit transistor density. In some embodiments, the nanowire body may have a thickness in the range of 1 to 20 nm and a length in the range of 5 to 100 nm.

公开(公告)号：US11222921B2

公开(公告)日：2022-01-11

申请号：US16635111

申请日：2017-08-29

Applicant: Intel Corporation

Inventor： Abhishek A. Sharma ,  Ravi Pillarisetty ,  Van H. Le ,  Gilbert W. Dewey ,  Willy Rachmady

IPC: H01L27/24 ,  H01L27/22 ,  H01L43/02 ,  H01L43/08 ,  H01L43/10 ,  H01L43/12 ,  H01L45/00

Abstract: Disclosed herein are selector devices and related devices and techniques. In some embodiments, a selector device may include a first electrode, a second electrode, and a selector material between the first electrode and the second electrode. The selector material may include a dielectric material and a conductive dopant.

公开(公告)号：US11152514B2

公开(公告)日：2021-10-19

申请号：US16640340

申请日：2017-09-29

Applicant: INTEL CORPORATION

Inventor： Van H. Le ,  Abhishek A. Sharma ,  Gilbert Dewey ,  Kent Millard ,  Jack Kavalieros ,  Shriram Shivaraman ,  Tristan A. Tronic ,  Sanaz Gardner ,  Justin R. Weber ,  Tahir Ghani ,  Li Huey Tan ,  Kevin Lin

IPC: H01L29/786 ,  H01L27/12 ,  H01L29/66 ,  H01L29/267

Abstract: Described is an apparatus which comprises: a gate comprising a metal; a first layer adjacent to the gate, the first layer comprising a dielectric material; a second layer adjacent to the first layer, the second layer comprising a second material; a third layer adjacent to the second layer, the third layer comprising a third material including an amorphous metal oxide; a fourth layer adjacent to the third layer, the fourth layer comprising a fourth material, wherein the fourth and second materials are different than the third material; a source partially adjacent to the fourth layer; and a drain partially adjacent to the fourth layer.

公开(公告)号：US11139296B2

公开(公告)日：2021-10-05

申请号：US15941384

申请日：2018-03-30

Applicant: Intel Corporation

Inventor： Abhishek A. Sharma ,  Van H. Le ,  Gilbert Dewey ,  Willy Rachmady ,  Ravi Pillarisetty

IPC: H01L27/092 ,  H01L27/12 ,  H01L23/528 ,  H01L29/24 ,  H01L29/423 ,  H01L29/66 ,  H01L29/786 ,  H01L21/8238 ,  H01L21/02

Abstract: Techniques and mechanisms for providing a space efficient complementary metal-oxide-semiconductor (CMOS) circuit. In an embodiment, a p-type transistor of a circuit is to conduct current in a direction parallel to a surface of a semiconductor substrate, wherein an n-type thin film transistor (TFT) of the circuit is to conduct current in a direction which is orthogonal to the surface. A first interconnect is directly coupled to each of the two transistors, wherein the first interconnect, a high mobility channel structure of the n-type TFT, and a source or drain of the p-type transistor are on the same line of direction. A second interconnect comprises a conductive path which extends to respective gates of the p-type transistor and the n-type TFT, wherein the conductive path is limited to a region over a footprint of the p-type transistor. In another embodiment, functionality of a logical inverter is provided with the circuit.

公开(公告)号：US11127861B2

公开(公告)日：2021-09-21

申请号：US16633614

申请日：2017-09-27

Applicant: Intel Corporation

Inventor： Abhishek A. Sharma

IPC: G11C16/04 ,  H01L29/792 ,  G11C16/10 ,  G11C16/26 ,  H01L29/417 ,  H01L29/49 ,  H01L29/786

Abstract: An embodiment includes an apparatus comprising: a thin film transistor (TFT) comprising: source and drain contacts; first and second gate contacts: a semiconductor material, comprising a channel, between the first and second gate contacts; and a first dielectric layer, between the first and second gate contacts, to fix charged particles. Other embodiments are described herein.

公开(公告)号：US11075207B2

公开(公告)日：2021-07-27

申请号：US16633061

申请日：2017-09-29

Applicant: INTEL CORPORATION

Inventor： Abhishek A. Sharma ,  Brian S. Doyle ,  Ravi Pillarisetty ,  Prashant Majhi

IPC: G11C11/00 ,  H01L27/11 ,  G11C5/06 ,  G11C5/10 ,  G11C11/419

Abstract: A 2T-2S SRAM cell exhibiting a complementary scheme, that includes two selector devices that exhibit negative differential resistance. Advantages include lower area and better performance than traditional SRAM cells, according to some embodiments. The term 1T-1S refers to a transistor in series with a selector device. Accordingly, the term 2T-2S refers to two such 1T-1S structures.

公开(公告)号：US11031072B2

公开(公告)日：2021-06-08

申请号：US16641574

申请日：2017-09-28

Applicant: Intel Corporation

Inventor： Abhishek A. Sharma ,  Ravi Pillarisetty ,  Brian S. Doyle ,  Prashant Majhi

IPC: G11C11/00 ,  G11C11/56 ,  H01L45/00 ,  H01L47/00 ,  H01L27/24 ,  G11C13/00 ,  G11C11/4096 ,  H01L27/108 ,  G11C14/00 ,  G11C11/40

Abstract: Described herein are apparatuses, systems, and methods associated with a memory circuit that includes memory cells having respective threshold switches. The memory cells may include a selector transistor with a gate terminal coupled to a word line to receive a word line signal, a drain terminal coupled to a bit line to receive a bit line signal, and a source terminal coupled to a first terminal of the threshold switch. The threshold switch may switch from a high resistance state to a low resistance state when a voltage across the first terminal and a second terminal exceeds a threshold voltage and may remain in the low resistance state after switching when the voltage across the first and second terminals is equal to or greater than a holding voltage that is less than the threshold voltage. Other embodiments may be described and claimed.

公开(公告)号：US20210013208A1

公开(公告)日：2021-01-14

申请号：US16630550

申请日：2017-09-14

Applicant: Intel Corporation

Inventor： Van H. Le ,  Ravi Pillarisetty ,  Abhishek A. Sharma

IPC: H01L27/102 ,  H01L29/06 ,  H01L29/423 ,  H01L29/747

Abstract: Disclosed herein are gated thyristors and related devices and techniques. In some embodiments, an integrated circuit (IC) device may include a metal portion and a gated thyristor on the metal portion. The gated thyristor may include a stack of alternating p-type and n-type material layers, and the stack may be on the metal portion. The IC device may further include a gate line spaced apart from one of the material layers by a gate dielectric.