公开(公告)号：US09965375B2

公开(公告)日：2018-05-08

申请号：US15194881

申请日：2016-06-28

Applicant: INTEL CORPORATION

Inventor： Matthew C. Merten ,  Beeman C. Strong ,  Michael W. Chynoweth ,  Grant G. Zhou ,  Andreas Kleen ,  Kimberly C. Weier ,  Angela D. Schmid ,  Stanislav Bratanov ,  Seth Abraham ,  Jason W. Brandt ,  Ahmad Yasin

IPC: G06F11/36 ,  G06F9/455 ,  H04L12/26 ,  H04L12/24

CPC classification number: G06F11/3636 ,  G06F9/45558 ,  G06F2009/45591 ,  H04L41/0613 ,  H04L43/04

Abstract: A core includes a memory buffer and executes an instruction within a virtual machine. A processor tracer captures trace data and formats the trace data as trace data packets. An event-based sampler generates field data for a sampling record in response to occurrence of an event of a certain type as a result of execution of the instruction. The processor tracer, upon receipt of the field data: formats the field data into elements of the sampling record as a group of record packets; inserts the group of record packets between the trace data packets as a combined packet stream; and stores the combined packet stream in the memory buffer as a series of output pages. The core, when in guest profiling mode, executes a virtual machine monitor to map output pages of the memory buffer to host physical pages of main memory using multilevel page tables.

公开(公告)号：US20180088861A1

公开(公告)日：2018-03-29

申请号：US15277855

申请日：2016-09-27

Applicant: Intel Corporation

Inventor： Ahmad Yasin ,  Stanislav Bratanov

IPC: G06F3/06 ,  G06F12/0875 ,  G06F9/38 ,  G06F11/30

CPC classification number: G06F3/0656 ,  G06F3/061 ,  G06F3/0683 ,  G06F9/30 ,  G06F9/3802 ,  G06F11/3024 ,  G06F11/3466 ,  G06F12/0875

Abstract: Systems and method are disclosed for monitoring processor performance. Embodiments described relate to differentiating function performance by input parameters. In one embodiment, a method includes configuring a counter contained in a processor to count occurrences of an event in the processor and to overflow upon the count of occurrences reaching a specified value, configuring a precise event based sampling (PEBS) handler circuit to generate and store a PEBS record into a PEBS memory buffer after at least one overflow, the PEBS record containing at least one stack entry read from a stack after the at least one overflow, enabling the PEBS handler circuit to generate and store the PEBS record after the at least one overflow, generating and storing the PEBS record into the PEBS memory buffer after the at least one overflow; and storing contents of the PEBS memory buffer to a PEBS trace file in a memory.

公开(公告)号：US09916161B2

公开(公告)日：2018-03-13

申请号：US14750535

申请日：2015-06-25

Applicant: Intel Corporation

Inventor： Ahmad Yasin

IPC: G06F9/30 ,  G06F9/38 ,  G06F11/30

CPC classification number: G06F9/30076 ,  G06F9/3836 ,  G06F11/30

Abstract: A processor includes a front end, an execution unit, a retirement stage, a counter, and a performance monitoring unit. The front end includes logic to receive an event instruction to enable supervision of a front end event that will delay execution of instructions. The execution unit includes logic to set a register with parameters for supervision of the front end event. The front end further includes logic to receive a candidate instruction and match the candidate instruction to the front end event. The counter includes logic to generate the front end event upon retirement of the candidate instruction.

公开(公告)号：US09671853B2

公开(公告)日：2017-06-06

申请号：US14484649

申请日：2014-09-12

Applicant: Intel Corporation

Inventor： Yoni Aizik ,  Eliezer Weissmann ,  Efraim Rotem ,  Yevgeni Sabin ,  Doron Rajwan ,  Ahmad Yasin

IPC: G06F1/32

CPC classification number: G06F1/324 ,  G06F1/3296 ,  Y02D10/126 ,  Y02D10/172

Abstract: In an embodiment, a processor includes at least one core and energy performance gain (EPG) logic to determine an EPG frequency based on a first value of an EPG. The EPG is based upon energy consumed by the processor and upon performance of the processor. The processor also includes a clock generator to generate a frequency of operation of the at least one core based on the EPG frequency. Other embodiments are described and claimed.

公开(公告)号：US20160378470A1

公开(公告)日：2016-12-29

申请号：US14750535

申请日：2015-06-25

Applicant: Intel Corporation

Inventor： Ahmad Yasin

IPC: G06F9/30

CPC classification number: G06F9/30076 ,  G06F9/3836 ,  G06F11/30

Abstract: A processor includes a front end, an execution unit, a retirement stage, a counter, and a performance monitoring unit. The front end includes logic to receive an event instruction to enable supervision of a front end event that will delay execution of instructions. The execution unit includes logic to set a register with parameters for supervision of the front end event. The front end further includes logic to receive a candidate instruction and match the candidate instruction to the front end event. The counter includes logic to generate the front end event upon retirement of the candidate instruction.

Abstract translation: 处理器包括前端，执行单元，退休阶段，计数器和性能监视单元。 前端包括接收事件指令以允许监视将延迟执行指令的前端事件的逻辑。 执行单元包括用于设置具有用于监视前端事件的参数的寄存器的逻辑。 前端还包括接收候选指令并将候选指令与前端事件相匹配的逻辑。 计数器包括在退出候选指令时产生前端事件的逻辑。

公开(公告)号：US20160077569A1

公开(公告)日：2016-03-17

申请号：US14484649

申请日：2014-09-12

Applicant: Intel Corporation

Inventor： Yoni Aizik ,  Eliezer Weissmann ,  Efraim Rotem ,  Yevgeni Sabin ,  Doron Rajwan ,  Ahmad Yasin

IPC: G06F1/32 ,  G06F1/28

CPC classification number: G06F1/324 ,  G06F1/3296 ,  Y02D10/126 ,  Y02D10/172

Abstract: In an embodiment, a processor includes at least one core and energy performance gain (EPG) logic to determine an EPG frequency based on a first value of an EPG. The EPG is based upon energy consumed by the processor and upon performance of the processor. The processor also includes a clock generator to generate a frequency of operation of the at least one core based on the EPG frequency. Other embodiments are described and claimed.

Abstract translation: 在一个实施例中，处理器包括至少一个核心和能量性能增益（EPG）逻辑，以基于EPG的第一值来确定EPG频率。 EPG基于处理器消耗的能量和处理器的性能。 处理器还包括时钟发生器，用于基于EPG频率产生至少一个核心的操作频率。 描述和要求保护其他实施例。

公开(公告)号：US12229558B2

公开(公告)日：2025-02-18

申请号：US18473088

申请日：2023-09-22

Applicant: Intel Corporation

Inventor： Ahmad Yasin

IPC: G06F9/30 ,  G06F9/38 ,  G06F11/30

Abstract: A processor includes a front end, an execution unit, a retirement stage, a counter, and a performance monitoring unit. The front end includes logic to receive an event instruction to enable supervision of a front end event that will delay execution of instructions. The execution unit includes logic to set a register with parameters for supervision of the front end event. The front end further includes logic to receive a candidate instruction and match the candidate instruction to the front end event. The counter includes logic to generate the front end event upon retirement of the candidate instruction.

公开(公告)号：US12216932B2

公开(公告)日：2025-02-04

申请号：US18327474

申请日：2023-06-01

Applicant: Intel Corporation

Inventor： Ahmad Yasin ,  Michael Chynoweth ,  Rajshree Chabukswar ,  Muhammad Taher

IPC: G06F3/06 ,  G06F11/34

Abstract: A processor includes a memory subunit that includes a status register and an execution engine unit to: randomly select a load operation to monitor; determine a re-order buffer identifier of the load operation; and transmit the re-order buffer identifier to the memory subsystem. Responsive to receipt of the re-order buffer identifier, the first memory subunit is to store a piece of information, related to a status of the load operation, in the status register. The processor also includes logic to, responsive to detection of retirement of the load operation, store memory information in memory-related fields of a record of a memory buffer. The memory information includes auxiliary information (AUX) and access latency information, wherein one of the auxiliary information or the access latency information includes the piece of information, from the status register, stored in a particular field of the memory-related fields.

公开(公告)号：US20240111654A1

公开(公告)日：2024-04-04

申请号：US18374296

申请日：2023-09-28

Applicant: Intel Corporation

Inventor： Raoul Rivas Toledano ,  Udayan Kapaley ,  Ahmad Yasin ,  Karthik Gopalakrishnan ,  Marc Torrant

IPC: G06F11/34 ,  G06F9/30

CPC classification number: G06F11/3466 ,  G06F9/30145 ,  G06F11/3409

Abstract: Detailed herein are examples of hybrid (heterogenous) performance monitoring unit enumeration. In some examples, a processor supports an instruction that enumerates performance monitoring unit enumeration. For example, the processor comprises decoder circuitry to decode an instance of a single instruction, the single instruction to include a field for an opcode; and execution circuitry to execute the decoded instruction according to the opcode to return the processor identification and feature information including an enumeration of heterogenous performance monitoring unit capabilities.

公开(公告)号：US10795684B2

公开(公告)日：2020-10-06

申请号：US15200326

申请日：2016-07-01

Applicant: Intel Corporation

Inventor： Ahmad Yasin ,  Eti Pardo-Fridman ,  Ofer Levy

IPC: G06F9/38 ,  G06F11/30 ,  G06F12/08 ,  G06F1/324 ,  G06F11/34 ,  G06F9/30 ,  G06F12/0897 ,  G06F12/1027 ,  G06F12/0875

Abstract: A processor includes a front end including circuitry to decode an instruction from an instruction stream and a core including circuitry to process the instruction. The core includes an execution pipeline, a dynamic core frequency logic unit, and a counter compensation logic unit. The execution pipeline includes circuitry to execute the instruction. The dynamic core frequency logic unit includes circuitry to squash a clock of the core to reduce a core frequency. The clock may not be visible to software. The counter compensation logic unit includes circuitry to adjust a performance counter increment associated with a performance counter based on at least the dynamic core frequency logic unit circuitry to squash a clock of the core to reduce a core frequency.