公开(公告)号：US20240105811A1

公开(公告)日：2024-03-28

申请号：US17955209

申请日：2022-09-28

Applicant: Intel Corporation

Inventor： Abhishek Anil Sharma ,  Sagar Suthram ,  Tahir Ghani ,  Anand Murthy ,  Wilfred Gomes ,  Pushkar Ranade

IPC: H01L29/51 ,  H01L21/28 ,  H01L27/11507 ,  H01L27/1159

CPC classification number: H01L29/516 ,  H01L27/11507 ,  H01L27/1159 ,  H01L29/40111 ,  G11C11/221

Abstract: An integrated circuit (IC) die includes a plurality of ferroelectric tunnel junction (FTJ) devices, where at least one FTJ of the plurality of FTJ devices comprises first electrode, a second electrode, ferroelectric material disposed between the first and second electrodes, and interface material disposed between at least one of the first and second electrodes and the ferroelectric material. Other embodiments are disclosed and claimed.

公开(公告)号：US20240105585A1

公开(公告)日：2024-03-28

申请号：US17955245

申请日：2022-09-28

Applicant: Intel Corporation

Inventor： Abhishek Anil Sharma ,  Pushkar Ranade ,  Tahir Ghani ,  Wilfred Gomes ,  Sagar Suthram ,  Anand Murthy

IPC: H01L23/522 ,  H01L23/427

CPC classification number: H01L23/5223 ,  H01L23/427

Abstract: An embodiment of a capacitor in the back-side layers of an IC die may comprise any type of solid-state electrolyte material disposed between electrodes of the capacitor. Another embodiment of a capacitor anywhere in an IC die may include one or more materials selected from the group of indium oxide, indium nitride, gallium oxide, gallium nitride, zinc oxide, zinc nitride, tungsten oxide, tungsten nitride, tin oxide, tin nitride, nickel oxide, nickel nitride, niobium oxide, niobium nitride, cobalt oxide, and cobalt nitride between electrodes of the capacitor. Other embodiments are disclosed and claimed.

公开(公告)号：US20240008285A1

公开(公告)日：2024-01-04

申请号：US17856877

申请日：2022-07-01

Applicant: Intel Corporation

Inventor： Abhishek Anil Sharma ,  Anand Murthy ,  Wilfred Gomes ,  Tahir Ghani

IPC: H01L27/11514 ,  H01L29/78 ,  H01L29/66 ,  H01L29/06

CPC classification number: H01L27/11514 ,  H01L29/0673 ,  H01L29/6684 ,  H01L29/78391

Abstract: Bits are stored in an array with multiple capacitors sharing a single access transistor and a common plate coupled to the transistor. A single common select transistor accesses information stored in an array of capacitors, above and below the transistor and sharing a common plate. The common plate may be vertical and encircled by each of the other plates. The capacitors may be ferroelectric capacitors. In an integrated circuit system, the array may be coupled to a power supply and a cooling structure.

公开(公告)号：US20240008244A1

公开(公告)日：2024-01-04

申请号：US17856879

申请日：2022-07-01

Applicant: Intel Corporation

Inventor： Abhishek Anil Sharma ,  Sagar Suthram ,  Wilfred Gomes ,  Anand Murthy ,  Tahir Ghani

IPC: H01L27/108

CPC classification number: H01L27/108

Abstract: Bits are stored in cells having two transistors between two parallel bitlines. In a memory array, first and second transistor channels in a bit cell are parallel and offset and coupled to first and second bitlines, respectively, which are also parallel and offset. Adjacent bit cells share corresponding transistor channel structures. The transistor channels may be orthogonal to the bitlines. The memory array may be on an integrated circuit (IC) die, which may be coupled to a power supply in an IC system. In an IC system, the memory array may be coupled to a power supply and a cooling structure.

公开(公告)号：US20230197825A1

公开(公告)日：2023-06-22

申请号：US17555247

申请日：2021-12-17

Applicant: Intel Corporation

Inventor： Prashant Majhi ,  Anand Murthy

IPC: H01L29/45

CPC classification number: H01L29/456 ,  H01L29/7851

Abstract: Transition metal dichalcogenide (TMD) monolayers are positioned between a contact metal and a semiconductor to pin the Fermi level at the metal-semiconductor interface. The pinned Fermi level can provide for a lower Schottky barrier height between the contact metal and semiconductor than if no TMD were present at the contact metal-semiconductor interface. The height of the Schottky barrier can be tuned through the selection of the transition metal dichalcogenide used for the monolayer. Transition metal dichalcogenides have the chemical formula MX2, where M is a transition metal and X=sulfur, selenium, or tellurium. The transition metal dichalcogenides used for metal contact-semiconductor interfaces can have M=titanium, platinum, molybdenum, tungsten, erbium, rhodium, or lanthanum. A lower Schottky barrier height can reduce contact resistance, which can improve transistor performance as the parasitic resistance of source/drain channels approach that of transistor channel as transistor geometries continued to scale.

公开(公告)号：US20230197729A1

公开(公告)日：2023-06-22

申请号：US18108526

申请日：2023-02-10

Applicant: Intel Corporation

Inventor： Anand Murthy ,  Ryan Keech ,  Nicholas G. Minutillo ,  Ritesh Jhaveri

IPC: H01L27/092 ,  H01L29/66 ,  H01L29/51 ,  H01L29/78 ,  H01L29/08 ,  H01L29/49 ,  H01L29/167 ,  H01L21/8238 ,  H01L29/06 ,  H01L29/10

CPC classification number: H01L27/0924 ,  H01L29/66545 ,  H01L29/518 ,  H01L29/785 ,  H01L29/0847 ,  H01L29/4966 ,  H01L29/167 ,  H01L21/823871 ,  H01L21/823821 ,  H01L29/0673 ,  H01L29/1037 ,  H01L2029/7858

Abstract: Techniques are disclosed for providing an integrated circuit structure having NMOS transistors including an arsenic-doped interface layer between epitaxially grown source/drain regions and a channel region. The arsenic-doped interface layer may include, for example, arsenic-doped silicon (Si:As) having arsenic concentrations in a range of about 1E20 atoms per cm3 to about 5E21 atoms per cm3. The interface layer may have a relatively uniform thickness in a range of about 0.5 nm to full fill where the entire source/drain region is composed of the Si:As. In cases where the arsenic-doped interface layer only partially fills the source/drain regions, another n-type doped semiconductor material can fill remainder (e.g., phosphorus-doped III-V compound or silicon). The use of a layer having a high arsenic concentration can provide improved NMOS performance in the form of abrupt junctions in the source/drain regions and highly conductive source/drain regions with negligible diffusion of arsenic into the channel region.

公开(公告)号：US20230197568A1

公开(公告)日：2023-06-22

申请号：US17556520

申请日：2021-12-20

Applicant: Intel Corporation

Inventor： Prashant Majhi ,  Anand Murthy

IPC: H01L23/48 ,  H01L23/498 ,  H01L49/02 ,  H01L21/48 ,  H01L21/768

CPC classification number: H01L23/481 ,  H01L23/49838 ,  H01L23/49827 ,  H01L28/75 ,  H01L28/92 ,  H01L21/486 ,  H01L21/76898 ,  H01L25/0655

Abstract: An apparatus includes a first layer comprising silicon, and a conductive feature extending within the silicon of the first layer. The conductive feature includes (i) conductive material extending throughout the length of the conductive feature, (ii) a barrier layer between the conductive material and the silicon of the first layer, and (iii) a second layer including dielectric material between the barrier layer and the silicon of the first layer. In an example, one or more discontinuous monolayers of metal are between sections of the dielectric material and the silicon of the first layer. The conductive feature is formed in a recess extending within the silicon of the first layer. In an example, the recess is formed using a metal assisted etch process using the metal as a catalyst, and one or more discontinuous monolayers of the metal are remnants of the metal used in the metal assisted etch process.

公开(公告)号：US20220415708A1

公开(公告)日：2022-12-29

申请号：US17358903

申请日：2021-06-25

Applicant: Intel Corporation

Inventor： Rishabh Mehandru ,  Stephen Cea ,  Tahir Ghani ,  Patrick Keys ,  Aaron Lilak ,  Anand Murthy ,  Cory Weber

IPC: H01L21/768 ,  H01L29/10 ,  H01L27/088 ,  H01L25/07 ,  H01L29/66 ,  H01L29/78

Abstract: Integrated circuitry comprising transistor structures with a source/drain etch stop layer to limit the depth of source and drain material relative to a channel of the transistor. A portion of a channel material layer may be etched in preparation for source and drain materials. The etch may be stopped at an etch stop layer buried between a channel material layer and an underlying planar substrate layer. The etch stop layer may have a different composition than the channel layer while retaining crystallinity of the channel layer. The source and drain etch stop layer may provide adequate etch selectivity to ensure a source and drain etch process does not punch through the etch stop layer. Following the etch process, source and drain materials may be formed, for example with an epitaxial growth process. The source and drain etch stop layer may be, for example, primarily silicon and carbon.

公开(公告)号：US11521968B2

公开(公告)日：2022-12-06

申请号：US16024671

申请日：2018-06-29

Applicant: Intel Corporation

Inventor： Cory Bomberger ,  Anand Murthy ,  Stephen Cea ,  Biswajeet Guha ,  Anupama Bowonder ,  Tahir Ghani

IPC: H01L27/088 ,  H01L29/06 ,  H01L29/08 ,  H01L29/267 ,  H01L29/78 ,  H01L21/8234 ,  H01L29/66 ,  H01L27/092

Abstract: Embodiments of the disclosure are in the field of advanced integrated circuit structure fabrication and, in particular, integrated circuit structures having channel structures with sub-fin dopant diffusion blocking layers are described. In an example, an integrated circuit structure includes a fin having a lower fin portion and an upper fin portion. The lower fin portion includes a dopant diffusion blocking layer on a first semiconductor layer doped to a first conductivity type. The upper fin portion includes a portion of a second semiconductor layer, the second semiconductor layer on the dopant diffusion blocking layer. An isolation structure is along sidewalls of the lower fin portion. A gate stack is over a top of and along sidewalls of the upper fin portion, the gate stack having a first side opposite a second side. A first source or drain structure at the first side of the gate stack.

公开(公告)号：US20220199468A1

公开(公告)日：2022-06-23

申请号：US17133065

申请日：2020-12-23

Applicant: Intel Corporation

Inventor： Kimin Jun ,  Souvik Ghosh ,  Willy Rachmady ,  Ashish Agrawal ,  Siddharth Chouksey ,  Jessica Torres ,  Jack Kavalieros ,  Matthew Metz ,  Ryan Keech ,  Koustav Ganguly ,  Anand Murthy

IPC: H01L21/768 ,  H01L23/522 ,  H01L29/417 ,  H01L29/45 ,  H01L29/40 ,  H01L29/66 ,  H01L23/00 ,  H01L27/22 ,  H01L27/24

Abstract: An integrated circuit interconnect structure includes a metallization level above a first device level. The metallization level includes an interconnect structure coupled to the device structure, a conductive cap including an alloy of a metal of the interconnect structure and either silicon or germanium on an uppermost surface of the interconnect structure. A second device level above the conductive cap includes a transistor coupled with the conductive cap. The transistor includes a channel layer including a semiconductor material, where at least one sidewall of the conductive cap is co-planar with a sidewall of the channel layer. The transistor further includes a gate on a first portion of the channel layer, where the gate is between a source region and a drain region, where one of the source or the drain region is in contact with the conductive cap.