公开(公告)号：US20200312846A1

公开(公告)日：2020-10-01

申请号：US16649799

申请日：2017-12-29

Applicant: INTEL CORPORATION

Inventor： Willy Rachmady ,  Abhishek A. Sharma ,  Ravi Pillarisetty ,  Patrick Morrow ,  Rishabh Mehandru ,  Aaron D. Lilak ,  Gilbert Dewey ,  Cheng-Ying Huang

IPC: H01L27/092 ,  H01L29/20 ,  H01L29/06 ,  H01L29/417 ,  H01L29/66

Abstract: An integrated circuit includes: a germanium-containing fin structure above a layer of insulation material; a group III-V semiconductor material containing fin structure above the layer of insulation material; a first gate structure on a portion of the germanium-containing fin structure; a second gate structure on a portion of the group III-V semiconductor material containing fin structure; a first S/D region above the layer of insulation material and laterally adjacent to the portion of the germanium-containing fin structure, the first S/D region comprising a p-type impurity and at least one of silicon or germanium; a second S/D region above the layer of insulation material and laterally adjacent to the portion of the group III-V semiconductor material containing fin structure, the second S/D region comprising an n-type impurity and a second group III-V semiconductor material; and a layer comprising germanium between the layer of insulation material and the second S/D region.

公开(公告)号：US20200219970A1

公开(公告)日：2020-07-09

申请号：US16240156

申请日：2019-01-04

Applicant: Intel Corporation

Inventor： Ehren Mannebach ,  Anh Phan ,  Aaron Lilak ,  Willy Rachmady ,  Gilbert Dewey ,  Cheng-Ying Huang ,  Richard Schenker ,  Hui Jae Yoo ,  Patrick Morrow

IPC: H01L29/06 ,  H01L29/417 ,  H01L29/66 ,  H01L29/78 ,  H01L27/088

Abstract: Gate-all-around integrated circuit structures having depopulated channel structures, and methods of fabricating gate-all-around integrated circuit structures having depopulated channel structures using multiple bottom-up oxidation approaches, are described. For example, an integrated circuit structure includes a vertical arrangement of nanowires. All nanowires of the vertical arrangement of nanowires are oxide nanowires. A gate stack is over the vertical arrangement of nanowires, around each of the oxide nanowires. The gate stack includes a conductive gate electrode.

公开(公告)号：US10522510B2

公开(公告)日：2019-12-31

申请号：US15575323

申请日：2015-06-26

Applicant: Intel Corporation

Inventor： Kimin Jun ,  Jacob M. Jensen ,  Patrick Morrow ,  Paul B. Fischer

IPC: H01L25/00 ,  H01L25/065 ,  H01L25/07 ,  H01L25/16 ,  H01L23/00 ,  H01L21/683

Abstract: A method including coupling a device substrate to a carrier substrate; aligning a portion of the device substrate to a host substrate; separating the portion of the device substrate from the carrier substrate; and after separating the portion of the device substrate, coupling the portion of the device substrate to the host substrate. A method including coupling a device substrate to a carrier substrate with an adhesive between a device side of the device substrate and the carrier substrate; after coupling the device substrate to the carrier substrate, thinning the device substrate; aligning a portion of the thinned device substrate to a host substrate; separating the portion of the device substrate from the carrier substrate; and coupling the separated portion of the device substrate to the host substrate. An apparatus including a substrate including a submicron thickness and a device layer coupled to a host substrate in a stacked arrangement.

公开(公告)号：US20190333803A1

公开(公告)日：2019-10-31

申请号：US16475084

申请日：2017-03-30

Applicant: Intel Corporation

Inventor： Anup Pancholi ,  Prashant Majhi ,  Paul Fischer ,  Patrick Morrow

IPC: H01L21/762 ,  H01L23/00 ,  H01L23/522

Abstract: An apparatus is provided which comprises: a substrate; one or more active devices adjacent to the substrate; a first set of one or more layers to interconnect the one or more active devices; a second set of one or more layers; and a layer adjacent to one of the layers of the first and second sets, wherein the layer is to bond the one of the layers of the first and second sets.

公开(公告)号：US10304946B2

公开(公告)日：2019-05-28

申请号：US15570965

申请日：2015-06-17

Applicant: Intel Corporation

Inventor： Rishabh Mehandru ,  Patrick Morrow ,  Ranjith Kumar ,  Cory E. Weber ,  Seiyon Kim ,  Stephen M. Cea ,  Tahir Ghani

IPC: H01L29/66 ,  H01L29/78 ,  H01L21/822 ,  H01L21/8238 ,  H01L27/06 ,  H01L21/8234 ,  H01L21/84 ,  H01L27/108 ,  H01L27/12 ,  H01L27/11

Abstract: Vertical integration schemes and circuit elements architectures for area scaling of semiconductor devices are described. In an example, an inverter structure includes a semiconductor fin separated vertically into an upper region and a lower region. A first plurality of gate structures is included for controlling the upper region of the semiconductor fin. A second plurality of gate structures is included for controlling the lower region of the semiconductor fin. The second plurality of gate structures has a conductivity type opposite the conductivity type of the first plurality of gate structures.

公开(公告)号：US10236282B2

公开(公告)日：2019-03-19

申请号：US15026268

申请日：2013-12-18

Applicant: Intel Corporation

Inventor： Patrick Morrow ,  Kimin Jun ,  Il-Seok Son ,  Rajashree Baskaran ,  Paul B. Fischer

IPC: H01L27/02 ,  H01L21/8258 ,  H01L21/683 ,  H01L23/528 ,  H01L29/16 ,  H01L29/20 ,  H01L27/085

Abstract: An embodiment includes an apparatus comprising: a first layer, including a first semiconductor switching element, coupled to a first portion of a first bonding material; and a second layer, including a second semiconductor switching element, coupled to a second portion of a second bonding material; wherein (a) the first layer is over the second layer, (b) the first portion is directly connected to the second portion, and (c) first sidewalls of the first portion are unevenly serrated. Other embodiments are described herein.

公开(公告)号：US20190057950A1

公开(公告)日：2019-02-21

申请号：US16077568

申请日：2016-03-31

Applicant: Intel Corporation

Inventor： Brennen K. Mueller ,  Patrick Morrow ,  Paul B. Fischer ,  Kimin Jun

IPC: H01L23/00 ,  H01L23/528 ,  H01L27/088 ,  H01L23/522 ,  H01L21/8234 ,  H01L23/60 ,  H01L25/065

Abstract: An embodiment includes an apparatus comprising: a first device layer included in a top edge of a semiconductor substrate; metal layers, on the first device layer, including first and second metal layers; a second device layer on the metal layers; and additional metal layers on the second device layer; wherein the second device layer is not included in any semiconductor substrate. Other embodiments are described herein.

公开(公告)号：US20180286916A1

公开(公告)日：2018-10-04

申请号：US15575667

申请日：2015-06-02

Applicant: Intel Corporation

Inventor： Yih Wang ,  Patrick Morrow

IPC: H01L27/22 ,  H01L43/08 ,  H01L45/00 ,  H01L27/24 ,  H01L43/02

CPC classification number: H01L27/226 ,  G11C11/161 ,  G11C13/0002 ,  G11C2213/71 ,  H01L27/228 ,  H01L27/2436 ,  H01L27/2454 ,  H01L43/02 ,  H01L43/08 ,  H01L45/04 ,  H01L45/1233

Abstract: A microelectronic memory having metallization layers formed on a back side of a substrate, wherein the metallization layers on back side may be used for the formation of source lines and word lines. Such a configuration may allow for a reduction in bit cell area, a higher memory array density, and lower source line and word line resistances. Furthermore, such a configuration may also provide the flexibility to independently optimize interconnect performance for logic and memory circuits.

公开(公告)号：US10043797B2

公开(公告)日：2018-08-07

申请号：US15124808

申请日：2014-06-23

Applicant: INTEL CORPORATION

Inventor： Kimin Jun ,  Patrick Morrow

IPC: H01L29/00 ,  H01L27/088 ,  H01L29/775 ,  H01L27/06 ,  H01L29/66 ,  H01L29/423 ,  H01L29/792 ,  H01L21/8234 ,  H01L21/8238 ,  H01L23/528 ,  H01L27/092 ,  H01L29/06 ,  H01L29/78

CPC classification number: H01L27/088 ,  H01L21/823475 ,  H01L21/823487 ,  H01L21/823871 ,  H01L21/823885 ,  H01L23/528 ,  H01L27/0688 ,  H01L27/092 ,  H01L27/105 ,  H01L27/11273 ,  H01L28/00 ,  H01L29/0676 ,  H01L29/401 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/66545 ,  H01L29/66666 ,  H01L29/775 ,  H01L29/7827 ,  H01L29/7926

Abstract: Techniques are disclosed for forming vertical transistor architectures. In accordance with some embodiments, a semiconductor layer is disposed over a lower interconnect layer and patterned into a plurality of vertical semiconductor bodies (e.g., nanowires and/or other three-dimensional semiconductor structures) in a regular, semi-regular, or irregular array, as desired for a given target application or end-use. Thereafter, a gate layer surrounding the active channel portion of each (or some sub-set) of the vertical semiconductor bodies is formed, followed by an upper interconnect layer, in accordance with some embodiments. During processing, a given vertical semiconductor body optionally may be removed and, in accordance with some embodiments, either: (1) blanked to provide a dummy channel; or (2) replaced with an electrically conductive plug to provide a via or other inter-layer routing. Processing can be performed in multiple iterations, for example, to provide multi-level/stacked vertical transistor circuit architectures of any standard and/or custom configuration.

公开(公告)号：US09935191B2

公开(公告)日：2018-04-03

申请号：US15122627

申请日：2014-06-13

Applicant: Intel Corporation

Inventor： Kimin Jun ,  Sansaptak Dasgupta ,  Alejandro X. Levander ,  Patrick Morrow

IPC: H01L29/15 ,  H01L31/0256 ,  H01L29/778 ,  H01L29/20 ,  H01L21/02 ,  H01L21/78 ,  H01L29/04 ,  H01L29/205 ,  H01L29/66

CPC classification number: H01L29/7787 ,  H01L21/0254 ,  H01L21/02609 ,  H01L21/76254 ,  H01L21/7806 ,  H01L29/045 ,  H01L29/2003 ,  H01L29/205 ,  H01L29/66462 ,  H01L29/7781

Abstract: A method including forming a barrier layer on a polar compound semiconductor layer on a sacrificial substrate; coupling the sacrificial substrate to a carrier substrate to form a composite structure wherein the barrier layer is disposed between the polar compound semiconductor layer and the carrier substrate; separating the sacrificial substrate from the composite structure to expose the polar compound semiconductor layer; and forming at least one circuit device. An apparatus including a barrier layer on a substrate; a transistor device on the barrier layer; and a polar compound semiconductor layer disposed between the barrier layer and the transistor device, the polar compound semiconductor layer including a two-dimensional electron gas therein.