中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

151 records (took 0.026 seconds)

    MEMORY CELLS WITH NON-PLANAR FERROELECTRIC OR ANTIFERROELECTRIC MATERIALS
    31.
    发明申请
    MEMORY CELLS WITH NON-PLANAR FERROELECTRIC OR ANTIFERROELECTRIC MATERIALS 有权

    公开(公告)号：US20230008261A1

    公开(公告)日：2023-01-12

    申请号：US17372612

    申请日：2021-07-12

    Applicant: Intel Corporation

    Inventor： Abhishek A. Sharma ,  Van H. Le ,  Brian S. Doyle ,  Prashant Majhi

    IPC: H01L29/78 ,  H01L27/1159 ,  H01L29/423 ,  H01L29/786 ,  H01L21/28 ,  H01L29/66

    Abstract: Memory cells with non-planar memory materials that include FE or AFE materials are described. An example memory cell includes a transistor provided over a support structure, where a memory material is integrated with a transistor gate. The channel material and the memory material are non-planar in that each includes a horizontal portion substantially parallel to the support structure, and a first and a second sidewall portions, each of which is substantially perpendicular to the support structure, where the horizontal portion of the memory material is between the horizontal portion of the channel material and a gate electrode material of the transistor gate, the first sidewall of the memory material is between the first sidewall of the channel material and the gate electrode material, and the second sidewall of the memory material is between the second sidewall of the channel material and the gate electrode material.

    Metal filament memory cells
    32.
    发明授权
    Metal filament memory cells 有权

    公开(公告)号：US11430949B2

    公开(公告)日：2022-08-30

    申请号：US16324464

    申请日：2016-09-25

    Applicant: Intel Corporation

    Inventor： Ravi Pillarisetty ,  Elijah V. Karpov ,  Prashant Majhi ,  Niloy Mukherjee

    IPC: H01L45/00 ,  H01L23/528 ,  H01L27/24

    Abstract: Disclosed herein are metal filament memory cells, and related devices and techniques. In some embodiments, a memory cell may include: a transistor having a source/drain region; and a metal filament memory device including an active metal and an electrolyte; wherein the electrolyte is coupled between the active metal and the source/drain region when the transistor is an n-type metal oxide semiconductor (NMOS) transistor, and the active metal is coupled between the electrolyte and the source/drain region when the transistor is a p-type metal oxide semiconductor (PMOS) transistor.

    DECK SELECT TRANSISTOR FOR THREE-DIMENSIONAL CROSS POINT MEMORY
    34.
    发明申请
    DECK SELECT TRANSISTOR FOR THREE-DIMENSIONAL CROSS POINT MEMORY 有权

    公开(公告)号：US20220190035A1

    公开(公告)日：2022-06-16

    申请号：US17118377

    申请日：2020-12-10

    Applicant: Intel Corporation

    Inventor： Prashant Majhi ,  Derchang Kau ,  Max Hineman

    IPC: H01L27/24 ,  H01L29/24 ,  H01L29/786 ,  H01L21/02 ,  H01L29/66

    Abstract: A memory device structure includes a first plurality of line structures, where each line structure, in the first plurality of line structures, includes a first transistor channel. The memory device structure further includes a second plurality of line structures substantially orthogonal to the first plurality of line structures, where each line structure, in the second plurality of line structures, includes a second transistor channel A memory cell is at each cross-point between the first plurality of line structures and the second plurality of line structures.

    Deuterium-based passivation of non-planar transistor interfaces
    36.
    发明授权
    Deuterium-based passivation of non-planar transistor interfaces 有权

    公开(公告)号：US11094785B2

    公开(公告)日：2021-08-17

    申请号：US16876528

    申请日：2020-05-18

    Applicant: INTEL CORPORATION

    Inventor： Prashant Majhi ,  Glenn A. Glass ,  Anand S. Murthy ,  Tahir Ghani ,  Aravind S. Killampalli ,  Mark R. Brazier ,  Jaya P. Gupta

    IPC: H01L29/10 ,  H01L29/775 ,  H01L21/30 ,  H01L29/78 ,  H01L29/423 ,  H01L29/786 ,  H01L27/092 ,  H01L29/06 ,  H01L21/8238

    Abstract: Techniques are disclosed for deuterium-based passivation of non-planar transistor interfaces. In some cases, the techniques can include annealing an integrated circuit structure including the transistor in a range of temperatures, pressures, and times in an atmosphere that includes deuterium. In some instances, the anneal process may be performed at pressures of up to 50 atmospheres to increase the amount of deuterium that penetrates the integrated circuit structure and reaches the interfaces to be passivated. Interfaces to be passivated may include, for example, an interface between the transistor conductive channel and bordering transistor gate dielectric and/or an interface between sub-channel semiconductor and bordering shallow trench isolation oxides. Such interfaces are common locations of trap sites that may include impurities, incomplete bonds dangling bonds, and broken bonds, for example, and thus such interfaces can benefit from deuterium-based passivation to improve the performance and reliability of the transistor.

    1S-1T FERROELECTRIC MEMORY
    39.
    发明申请
    1S-1T FERROELECTRIC MEMORY 审中-公开

    公开(公告)号：US20200234750A1

    公开(公告)日：2020-07-23

    申请号：US16633060

    申请日：2017-09-29

    Applicant: INTEL CORPORATION

    Inventor： Abhishek A. Sharma ,  Brian S. Doyle ,  Ravi Pillarisetty ,  Prashant Majhi ,  Elijah V. Karpov

    IPC: G11C11/22 ,  H01L27/11585

    Abstract: A 1S-1T ferroelectric memory cell is provided that include a transistor and a two-terminal selector device. The transistor exhibits a low conductive state and a high conductive state (channel resistance), depending on drive voltage. The two-terminal selector device exhibits one of an ON-state and an OFF-state depending upon whether the transistor is in its low conductive state or its high conductive state. The transistor may be, for instance, a ferroelectric gate vertical transistor. Modulation of a polarization state of ferroelectric material of the vertical transistor may be utilized to switch the state of the selector device. The memory cell may thus selectively be operated in one of an ON-state and an OFF-state depending upon whether the selector device is in its ON-state or OFF-state.

Patent Agency Ranking