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    FABRICATION OF RECONFIGURABLE ARCHITECTURES USING FERROELECTRICS
    1.
    发明公开
    FABRICATION OF RECONFIGURABLE ARCHITECTURES USING FERROELECTRICS 审中-公开

    公开(公告)号：US20240113123A1

    公开(公告)日：2024-04-04

    申请号：US17957836

    申请日：2022-09-30

    Applicant: Intel Corporation

    Inventor： Elijah V. Karpov ,  Sou-Chi Chang

    IPC: H01L27/118

    CPC classification number: H01L27/11807 ,  H01L2027/11838

    Abstract: An apparatus is provided which comprises: a plurality of logic blocks comprising transistors on a substrate, the logic blocks to implement logic functions; a plurality of input/output (I/O) blocks connecting the logic blocks with components external to the apparatus; a plurality of interconnect layers comprising wires and vias surrounded by interlayer dielectric above the substrate, the wires and vias conductively coupling the plurality of logic blocks and the plurality of I/O blocks; a plurality of programmable switches to configure connections between the plurality of logic blocks and the plurality of I/O blocks; and a ferroelectric material in a capacitor coupled to the gate or on the gate dielectric itself of one or more of the transistors. Other embodiments are also disclosed and claimed.

    METALLIZATION STACKS WITH SELF-ALIGNED STAGGERED METAL LINES
    4.
    发明申请
    METALLIZATION STACKS WITH SELF-ALIGNED STAGGERED METAL LINES 有权

    公开(公告)号：US20220084942A1

    公开(公告)日：2022-03-17

    申请号：US17017735

    申请日：2020-09-11

    Applicant: Intel Corporation

    Inventor： Elijah V. Karpov ,  Christopher J. Jezewski ,  Manish Chandhok ,  Nafees A. Kabir ,  Matthew V. Metz

    IPC: H01L23/528 ,  H01L23/522 ,  H01L21/768

    Abstract: Methods for fabricating metallization stacks with one or more self-aligned staggered metal lines, and related semiconductor devices, are disclosed. Methods and devices are based on providing a spacer material conformal to bottom metal lines of a first layer of a metallization stack. By carefully designing parameters of the deposition process, the spacer material may be deposited in such a manner that, for each pair of adjacent bottom metal lines of the first layer, an opening in the spacer material is formed in a layer above the bottom metal lines (i.e., in the second layer of the metallization stack), the opening being substantially equidistant to the adjacent bottom metal lines of the first layer. Top metal lines are formed by filling the openings with an electrically conductive material, resulting in the top metal lines being self-aligned and staggered with respect to the bottom metal lines.

    Multilayer selector device with low leakage current
    5.
    发明授权
    Multilayer selector device with low leakage current 有权

    公开(公告)号：US10825861B2

    公开(公告)日：2020-11-03

    申请号：US16077603

    申请日：2016-03-31

    Applicant: Intel Corporation

    Inventor： Elijah V. Karpov ,  Prashant Majhi ,  Ravi Pillarisetty ,  Uday Shah ,  James S. Clarke

    IPC: H01L27/24 ,  H01L45/00 ,  G11C13/00

    Abstract: An embodiment includes an apparatus comprising: first and second electrodes; first and second insulation layers between the first and second electrodes; and a middle layer between the first and second insulation layers; wherein (a) the middle layer includes material that has a first resistance when the first electrode is biased at a first voltage level and a second resistance when the first electrode is biased at a second voltage level; (b) the first resistance is less than the second resistance and the first voltage level is greater than the second voltage level. Other embodiments are described herein.

    Non-volatile memory devices including integrated ballast resistor
    7.
    发明授权
    Non-volatile memory devices including integrated ballast resistor 有权

    公开(公告)号：US10424620B2

    公开(公告)日：2019-09-24

    申请号：US15777535

    申请日：2015-12-23

    Applicant: INTEL CORPORATION

    Inventor： Prashant Majhi ,  Elijah V. Karpov ,  Ravi Pillarisetty ,  Uday Shah ,  Niloy Mukherjee

    IPC: H01L27/24 ,  H01L45/00 ,  G11C11/16 ,  H01L27/22 ,  H01L43/02 ,  H01L43/10 ,  G11C13/00

    Abstract: A non-volatile memory device is disclosed, in which a ballast resistor layer is disposed between the selector element and memory element of a given memory cell of the device. The material composition of the ballast resistor can be customized, as desired, and in some cases may be, for example, a sub-stoichiometric oxide of hafnium oxide (HfOx), tantalum oxide (TaOx), or titanium dioxide (TiOx), or an alloy of any thereof. In accordance with some embodiments, the integrated ballast resistor may serve the function of damping current surge related to the snapback characteristics of the selector element, preserving control of memory element switching. In accordance with some embodiments, an integrated ballast resistor layer provided as described herein may be implemented, for example, in any of a wide range of resistive random-access memory (RRAM) architectures and spin-transfer torque magnetic random-access memory (STTMRAM) architectures, including cross-point implementations of these types of architectures.

    MULTILAYER SELECTOR DEVICE WITH LOW LEAKAGE CURRENT
    8.
    发明申请
    MULTILAYER SELECTOR DEVICE WITH LOW LEAKAGE CURRENT 审中-公开

    公开(公告)号：US20190058006A1

    公开(公告)日：2019-02-21

    申请号：US16077603

    申请日：2016-03-31

    Applicant: Intel Corporation

    Inventor： Elijah V. Karpov ,  Prashant Majhi ,  Ravi Pillarisetty ,  Uday Shah ,  James S. Clarke

    IPC: H01L27/24 ,  H01L45/00

    Abstract: An embodiment includes an apparatus comprising: first and second electrodes; first and second insulation layers between the first and second electrodes; and a middle layer between the first and second insulation layers; wherein (a) the middle layer includes material that has a first resistance when the first electrode is biased at a first voltage level and a second resistance when the first electrode is biased at a second voltage level; (b) the first resistance is less than the second resistance and the first voltage level is greater than the second voltage level. Other embodiments are described herein.

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