公开(公告)号：US20230089863A1

公开(公告)日：2023-03-23

申请号：US17991811

申请日：2022-11-21

Applicant: Intel Corporation

Inventor： Shelly Kishore ,  Nivedita Aggarwal ,  Vincent Zimmer

IPC: G06F21/54 ,  G06F21/57

Abstract: A mailbox register is provided in local memory of a processor device, the processor device connected to a host processor device by an interconnect. The processor device accesses the mailbox register to determine that a ready value in the mailbox register identifies that an executable has been written to the mailbox register by the host processor device. The processor device reads the executable from the mailbox register and executes the executable to generate a result. The processor device writes an execution finished value to the mailbox register based on execution of the executable by the processor circuitry, which the host processor device can read to identify that execution of the executable is complete.

公开(公告)号：US20210311818A1

公开(公告)日：2021-10-07

申请号：US17255109

申请日：2018-12-11

Applicant: INTEL CORPORATION

Inventor： Vincent Zimmer ,  Anil Agrawal ,  Dujian Wu ,  Shijian Ge ,  Zhenglong Wu

IPC: G06F11/07

Abstract: Systems, apparatuses and methods may provide for technology that handles failures in memory hardware (e.g., dynamic random access memory (DRAM)) via runtime post package repair. Such technology may include operations to perform a runtime post package repair in response to a memory hardware failure detected in the memory. In such an example, the runtime post package repair may be done after power up boot operations have been completed.

公开(公告)号：US11068276B2

公开(公告)日：2021-07-20

申请号：US16431444

申请日：2019-06-04

Applicant: Intel Corporation

Inventor： Jiewen Yao ,  Vincent Zimmer ,  Nicholas Adams ,  Willard Wiseman ,  Giri Mudusuru ,  Nuo Zhang

IPC: G06F9/00 ,  G06F15/177 ,  G06F9/4401 ,  G06F9/445 ,  G06F21/57

Abstract: The present disclosure is directed to controlled customization of silicon initialization. A device may comprise, for example, a boot module including a memory on which boot code is stored, the boot code including at least an initial boot block (IBB) module that is not customizable and a global platform database (GPD) module including customizable data. The IBB module may include a pointer indicating GPD module location. The customizable data may comprise configurable parameters and simple configuration language (SCL) to cause the device to execute at least one logical operation during execution of the boot code. The GPD module may further comprise a pointer indicating SCL location. The boot code may be executed upon activation of the device, which may cause the IBB module to load an interpreter for executing the SCL. The interpreter may also verify access request operations in the SCL are valid before executing the access request operations.

公开(公告)号：US20210109824A1

公开(公告)日：2021-04-15

申请号：US17132227

申请日：2020-12-23

Applicant: Intel Corporation

Inventor： Karunakara Kotary ,  Prashant Dewan ,  Vincent Zimmer ,  Rajesh Poornachandran

IPC: G06F11/14 ,  G06F9/4401 ,  G06F11/20

Abstract: An apparatus to facilitate data resiliency in a computer system platform is disclosed. The apparatus comprises a non-volatile memory to store data resiliency logic and one or more processors to execute the data resiliency logic to collect boot critical data from a plurality of platform components and store the data within the non-volatile memory

公开(公告)号：US20210026652A1

公开(公告)日：2021-01-28

申请号：US16642318

申请日：2017-09-26

Applicant: Intel Corporation

Inventor： Yah Wen Ho ,  Vincent Zimmer ,  Tung Lun Loo

IPC: G06F9/4401 ,  G06F13/42

Abstract: Methods and apparatus for boot time reduction in a processor and programmable logic device environment are disclosed. An example apparatus includes a multicore processor including a first core and a second core. A bootstrap processor is to initialize the first core into a standby mode and initialize the second core into a non-standby mode. A programmable logic device is to be programmed with instructions to be executed by the programmable logic device by the second core via a first connection initialized by the second core. The bootstrap processor is to, upon completion of the programming of the programmable logic device, initialize a data connection between the programmable logic device and the second core.

公开(公告)号：US20190042395A1

公开(公告)日：2019-02-07

申请号：US16145399

申请日：2018-09-28

Applicant: Intel Corporation

Inventor： Li Tian ,  Varun K. Venkatesan ,  Richard Kozlak ,  Priyanka Hegde ,  Vincent Zimmer ,  Rodolfo Esteves Jaramillo ,  Xiangyang Guo

IPC: G06F11/36 ,  G06F11/34 ,  G06F8/41 ,  G06F8/30

Abstract: Systems, apparatuses and methods may provide for technology that may profile a first low-level language code to identify a first latency of a first portion of the first low-level language code. The technology may map the first portion to a source portion of a source code based on an identification that the first portion is a low-level language code representation of the source portion. The source code may be a high-level language code. The technology may associate the first latency with the source portion based on the mapping.

公开(公告)号：US09600671B2

公开(公告)日：2017-03-21

申请号：US15164398

申请日：2016-05-25

Applicant: Intel Corporation

Inventor： Ting Ye ,  Qin Long ,  Vincent Zimmer

IPC: G06F21/57 ,  G06F21/45

CPC classification number: G06F21/575 ,  G06F21/45 ,  G06F2221/034 ,  G06F2221/2117 ,  G06F2221/2131

Abstract: Described herein is technology for restoring access to a user account. In particular, systems and methods for account recovery using a platform attestation credential are described. In some embodiments, the platform attestation credential is generated by an authentication device in a pre boot environment. A first copy of the platform attestation credential may be bound by an account management system to a user account. Access to the user account may subsequently be restored using a second copy of the platform attestation credential.

公开(公告)号：US08631259B2

公开(公告)日：2014-01-14

申请号：US13764245

申请日：2013-02-11

Applicant: Intel Corporation

Inventor： Michael Rothman ,  Glenn Hinton ,  Vincent Zimmer ,  Michael Kinney ,  Mark Doran

IPC: G06F9/24 ,  G06F15/177

CPC classification number: G06F1/3234 ,  G06F9/4418

Abstract: When transitioning from sleep mode to active mode, a processing system loads first stage resume content and second stage resume content into a volatile memory of the processing system. The first stage resume content may contain contextual data for a first program that was in use before the processing system transitioned to sleep mode. The second stage resume content may contain contextual data for another program that was in use before the processing system transitioned to sleep mode. The processing system may provide a user interface for the first program before all of the second stage resume content has been loaded into the volatile memory. Other embodiments are described and claimed.

Abstract translation: 当从睡眠模式转换到活动模式时，处理系统将第一级恢复内容和第二级恢复内容加载到处理系统的易失性存储器中。 第一阶段恢复内容可以包含在处理系统转换到睡眠模式之前正在使用的第一程序的上下文数据。 第二阶段恢复内容可以包含在处理系统转换到睡眠模式之前正在使用的另一程序的上下文数据。 处理系统可以在所有第二阶段恢复内容已经被加载到易失性存储器之前为第一程序提供用户界面。 描述和要求保护其他实施例。

公开(公告)号：US12293182B2

公开(公告)日：2025-05-06

申请号：US18522526

申请日：2023-11-29

Applicant: Intel Corporation

Inventor： Vincent Zimmer ,  Jiewen Yao

IPC: G06F8/71 ,  G06F8/65

Abstract: An embodiment of a semiconductor package apparatus may include technology to determine version information for a new firmware component, read dependency information corresponding to the firmware component, and determine if dependency is satisfied between the new firmware component and one or more other firmware components based on the version information and the dependency information of the new firmware component. Other embodiments are disclosed and claimed.

公开(公告)号：US12079612B2

公开(公告)日：2024-09-03

申请号：US17113771

申请日：2020-12-07

Applicant: Intel Corporation

Inventor： Subrata Banik ,  Vincent Zimmer ,  Rajaram Regupathy ,  Ravi Poovalur Rangarajan

IPC: G06F8/65 ,  G06F9/4401 ,  G06F9/48 ,  G06F9/50 ,  G06F15/78

CPC classification number: G06F8/65 ,  G06F9/4401 ,  G06F9/4843 ,  G06F9/5027 ,  G06F15/7807

Abstract: Systems, apparatuses and methods may provide for technology that identifies, during a first boot process, whether at least one task associated with at least one software program is set to occur in a single-threaded process or a multithreaded process, in response to the at least one task being set to occur in the multithreaded process, executing the at least one task in the multithreaded process during the first boot process, and in response to the at least one task being set to occur in the single-threaded process, executing the at least one task in the single-threaded process during the first boot process.