公开(公告)号：US20220406907A1

公开(公告)日：2022-12-22

申请号：US17821209

申请日：2022-08-22

Applicant: Intel Corporation

Inventor： Abhishek A. Sharma ,  Tahir Ghani ,  Jack T. Kavalieros ,  Gilbert W. Dewey ,  Van H. Le ,  Lawrence D. Wong ,  Christopher J. Jezewski

IPC: H01L29/417 ,  H01L29/786 ,  H01L29/66 ,  H01L29/423 ,  H01L29/49 ,  H01L23/29 ,  H01L29/78 ,  H01L29/45

Abstract: Disclosed herein are transistor electrode-channel arrangements, and related methods and devices. For example, in some embodiments, a transistor electrode-channel arrangement may include a channel material, source/drain electrodes provided over the channel material, and a sealant at least partially enclosing one or more of the source/drain electrodes, wherein the sealant includes one or more metallic conductive materials.

公开(公告)号：US11444205B2

公开(公告)日：2022-09-13

申请号：US16143001

申请日：2018-09-26

Applicant: Intel Corporation

Inventor： Arnab Sen Gupta ,  Matthew Metz ,  Benjamin Chu-Kung ,  Abhishek Sharma ,  Van H. Le ,  Miriam R. Reshotko ,  Christopher J. Jezewski ,  Ryan Arch ,  Ande Kitamura ,  Jack T. Kavalieros ,  Seung Hoon Sung ,  Lawrence Wong ,  Tahir Ghani

IPC: H01L29/786 ,  H01L23/31 ,  H01L29/45 ,  H01L29/40 ,  H01L29/66 ,  H01L27/24 ,  H01L27/108

Abstract: Embodiments herein describe techniques for a semiconductor device including a substrate and a transistor above the substrate. The transistor includes a channel layer above the substrate, a conductive contact stack above the substrate and in contact with the channel layer, and a gate electrode separated from the channel layer by a gate dielectric layer. The conductive contact stack may be a drain electrode or a source electrode. In detail, the conductive contact stack includes at least a metal layer, and at least a metal sealant layer to reduce hydrogen diffused into the channel layer through the conductive contact stack. Other embodiments may be described and/or claimed.

公开(公告)号：US11380617B2

公开(公告)日：2022-07-05

申请号：US15903304

申请日：2018-02-23

Applicant: Intel Corporation

Inventor： Christopher J. Jezewski ,  Jasmeet S. Chawla

IPC: H01L23/528 ,  H01L21/768 ,  H01L23/522 ,  H01L23/532 ,  H01L21/033 ,  H01L21/02 ,  H01L21/311

Abstract: Embodiments of the invention describe low capacitance interconnect structures for semiconductor devices and methods for manufacturing such devices. According to an embodiment of the invention, a low capacitance interconnect structure comprises an interlayer dielectric (ILD). First and second interconnect lines are disposed in the ILD in an alternating pattern. The top surfaces of the first interconnect lines may be recessed below the top surfaces of the second interconnect lines. Increases in the recess of the first interconnect lines decreases the line-to-line capacitance between neighboring interconnects. Further embodiments include utilizing different dielectric materials as etching caps above the first and second interconnect lines. The different materials may have a high selectivity over each other during an etching process. Accordingly, the alignment budget for contacts to individual interconnect lines is increased.

公开(公告)号：US11201114B2

公开(公告)日：2021-12-14

申请号：US16465119

申请日：2016-12-29

Applicant: Intel Corporation

Inventor： Kevin Lin ,  Christopher J. Jezewski ,  Richard F. Vreeland ,  Tristan A. Tronic

IPC: H01L23/522 ,  H01L21/768 ,  H01L27/01 ,  H01L49/02

Abstract: Methods/structures of forming thin film resistors using interconnect liner materials are described. Those methods/structures may include forming a first liner in a first trench, wherein the first trench is disposed in a dielectric layer that is disposed on a substrate. Forming a second liner in a second trench, wherein the second trench is adjacent the first trench, forming an interconnect material on the first liner in the first trench, adjusting a resistance value of the second liner, forming a first contact structure on a top surface of the interconnect material, and forming a second contact structure on the second liner.

公开(公告)号：US10937689B2

公开(公告)日：2021-03-02

申请号：US16465510

申请日：2016-12-30

Applicant: Intel Corporation

Inventor： Manish Chandhok ,  Satyarth Suri ,  Tristan A. Tronic ,  Christopher J. Jezewski ,  Richard E. Schenker

IPC: H01L21/768 ,  H01L23/522 ,  H01L21/02

Abstract: In one embodiment, a trench may be formed in a dielectric surface, and the trenched may be lined with a liner. The trench may be filled with a metal, and the metal may be recessed below an opening of the trench. The liner may be converted into a dielectric, and a hard mask may be deposited into the trench.

公开(公告)号：US20200303257A1

公开(公告)日：2020-09-24

申请号：US16651116

申请日：2018-01-12

Applicant: Intel Corporation

Inventor： Aaron D. Lilak ,  Christopher J. Jezewski ,  Willy Rachmady ,  Rishabh Mehandru ,  Gilbert Dewey ,  Anh Phan

IPC: H01L21/8234 ,  H01L29/78

Abstract: In an embodiment of the present disclosure, a device structure includes a fin structure, a gate on the fin structure, and a source and a drain on the fin structure, where the gate is between the source and the drain. The device structure further includes an insulator layer having a first insulator layer portion adjacent to a sidewall of the source, a second insulator layer portion adjacent to a sidewall of the drain, and a third insulator layer portion therebetween adjacent to a sidewall of the gate, and two or more stressor materials adjacent to the insulator layer. The stressor materials can be tensile or compressively stressed and may strain a channel under the gate.

公开(公告)号：US09997457B2

公开(公告)日：2018-06-12

申请号：US14137526

申请日：2013-12-20

Applicant: Intel Corporation

Inventor： Christopher J. Jezewski ,  Tejaswi K. Indukuri ,  Ramanan V. Chebiam ,  Colin T. Carver

IPC: H01L29/40 ,  H01L23/532 ,  H01L21/768 ,  H01L23/522 ,  H01L29/49 ,  H01L29/78

CPC classification number: H01L23/53209 ,  H01L21/76831 ,  H01L21/76843 ,  H01L21/76846 ,  H01L21/76847 ,  H01L21/76879 ,  H01L21/76882 ,  H01L21/76883 ,  H01L23/5226 ,  H01L23/53261 ,  H01L23/53266 ,  H01L23/53295 ,  H01L29/4966 ,  H01L29/7848 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An embodiment includes a metal interconnect structure, comprising: a dielectric layer disposed on a substrate; an opening in the dielectric layer, wherein the opening has sidewalls and exposes a conductive region of at least one of the substrate and an interconnect line; an adhesive layer, comprising manganese, disposed over the conductive region and on the sidewalls; and a fill material, comprising cobalt, within the opening and on a surface of the adhesion layer. Other embodiments are described herein.

公开(公告)号：US09887161B2

公开(公告)日：2018-02-06

申请号：US15225392

申请日：2016-08-01

Applicant: INTEL CORPORATION

Inventor： Christopher J. Jezewski ,  David J. Michalak ,  Kanwal Jit Singh ,  Alan M. Myers

IPC: H01L23/48 ,  H01L23/532 ,  H01L21/768 ,  H01L21/3105 ,  H01L21/311 ,  H01L23/528 ,  H01L21/02

CPC classification number: H01L23/5329 ,  H01L21/02203 ,  H01L21/3105 ,  H01L21/31111 ,  H01L21/31116 ,  H01L21/31144 ,  H01L21/76802 ,  H01L21/76808 ,  H01L21/7682 ,  H01L21/76822 ,  H01L21/76826 ,  H01L21/76838 ,  H01L23/528 ,  H01L23/53209 ,  H01L23/53223 ,  H01L23/53238 ,  H01L23/53257 ,  H01L23/53266 ,  H01L23/53295 ,  H01L2221/1047 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Techniques are disclosed for forming interconnects in porous dielectric materials. In accordance with some embodiments, the porosity of a host dielectric layer may be reduced temporarily by stuffing its pores with a sacrificial pore-stuffing material, such as titanium nitride (TiN), titanium dioxide (TiO2), or other suitable sacrificial material having a high etch selectivity compared to the metallization and dielectric material of the interconnect. After interconnect formation within the stuffed dielectric layer, the sacrificial pore-stuffing material can be removed from the pores of the host dielectric. In some cases, removal and curing can be performed with minimal or otherwise negligible effect on the dielectric constant (κ-value), leakage performance, and/or time-dependent dielectric breakdown (TDDB) properties of the host dielectric layer. Some embodiments can be utilized, for example, in processes involving atomic layer deposition (ALD)-based and/or chemical vapor deposition (CVD)-based backend metallization of highly porous, ultra-low-κ (ULK) dielectric materials.

公开(公告)号：US20160183604A1

公开(公告)日：2016-06-30

申请号：US15062867

申请日：2016-03-07

Applicant: Intel Corporation

Inventor： Ravi Pillarisetty ,  Sairam Agraharam ,  John S. Guzek ,  Christopher J. Jezewski

IPC: A41D1/00 ,  G06F17/30 ,  H04N5/44 ,  G06K9/62 ,  H04N5/225 ,  H04N5/232

CPC classification number: A41D1/002 ,  G06F16/58 ,  G06K9/6215 ,  H04N5/225 ,  H04N5/2252 ,  H04N5/23238 ,  H04N5/23293 ,  H04N5/44 ,  H04N2101/00

Abstract: A wearable image sensor is described. In one example an apparatus includes a camera attached to a garment to capture an image of a view of an area surrounding a user that is wearing the garment, the image including an item. A data interface is attached to the garment and coupled to the camera to send the camera image to an external device and to receive description information about the item from the external device. A power supply is attached to the garment and coupled to the camera and the data interface to power the camera and the data interface. The apparatus presents the received description information to a user of the garment.

Abstract translation: 描述了可戴式图像传感器。 在一个示例中，一种装置包括附接到衣服的照相机，以捕获穿着服装的使用者周围的区域的视图的图像，该图像包括物品。 将数据接口连接到衣服并且耦合到相机以将照相机图像发送到外部设备并从外部设备接收关于该物品的描述信息。 电源被连接到衣服并且耦合到相机和数据接口以为相机和数据接口供电。 该装置将接收到的描述信息呈现给服装的用户。

公开(公告)号：US20240162058A1

公开(公告)日：2024-05-16

申请号：US18423577

申请日：2024-01-26

Applicant: Intel Corporation

Inventor： Christopher J. Jezewski

IPC: H01L21/67 ,  H01J37/32 ,  H01L21/3213 ,  H01L21/683 ,  H01L23/528

CPC classification number: H01L21/67069 ,  H01J37/3255 ,  H01J37/32669 ,  H01J37/32715 ,  H01L21/32136 ,  H01L21/32139 ,  H01L21/6831 ,  H01L23/5283 ,  H01J2237/14 ,  H01L23/53228

Abstract: Disclosed herein are tools and methods for subtractively patterning metals. These tools and methods may permit the subtractive patterning of metal (e.g., copper, platinum, etc.) at pitches lower than those achievable by conventional etch tools and/or with aspect ratios greater than those achievable by conventional etch tools. The tools and methods disclosed herein may be cost-effective and appropriate for high-volume manufacturing, in contrast to conventional etch tools.