公开(公告)号：US20190288190A1

公开(公告)日：2019-09-19

申请号：US16430201

申请日：2019-06-03

Applicant: Intel Corporation

Inventor： Kaan Oguz ,  Kevin P. O'Brien ,  Christopher J. Wiegand ,  MD Tofizur Rahman ,  Brian S. Doyle ,  Mark L. Doczy ,  Oleg Golonzka ,  Tahir Ghani ,  Justin S. Brockman

IPC: H01L43/12 ,  G11C11/16 ,  H01L43/10 ,  H01F10/32 ,  H01F41/30 ,  H01L43/08

Abstract: MTJ material stacks, pSTTM devices employing such stacks, and computing platforms employing such pSTTM devices. In some embodiments, perpendicular MTJ material stacks include a multi-layered filter stack disposed between a fixed magnetic layer and an antiferromagnetic layer or synthetic antiferromagnetic (SAF) stack. In some embodiments, non-magnetic layers of the filter stack include at least one of Ta, Mo, Nb, W, or Hf. These transition metals may be in pure form or alloyed with other constituents.

公开(公告)号：US10418415B2

公开(公告)日：2019-09-17

申请号：US16069165

申请日：2016-03-28

Applicant: Intel Corporation

Inventor： Christopher J. Wiegand ,  Oleg Golonzka ,  MD Tofizur Rahman ,  Brian S. Doyle ,  Mark L. Doczy ,  Kevin P. O'Brien ,  Kaan Oguz ,  Tahir Ghani ,  Satyarth Suri

IPC: H01L27/22 ,  H01L43/02 ,  H01L43/10 ,  H01L43/12 ,  G11C11/16 ,  H01F10/32 ,  H01F41/32 ,  H01L21/768 ,  H01L23/528 ,  H01L23/532 ,  H01L21/027 ,  H01L21/311 ,  H01L21/321 ,  H01L21/3213

Abstract: Approaches for an interconnect cladding process for integrating magnetic random access memory (MRAM) devices, and the resulting structures, are described. In an example, a memory structure includes an interconnect disposed in a trench of a dielectric layer above a substrate, the interconnect including a diffusion barrier layer disposed at a bottom of and along sidewalls of the trench to an uppermost surface of the dielectric layer, a conductive fill layer disposed on the diffusion barrier layer and recessed below the uppermost surface of the dielectric layer and an uppermost surface of the diffusion barrier layer, and a conductive capping layer disposed on the conductive fill layer and between sidewall portions of the diffusion barrier layer. A memory element is disposed on the conductive capping layer of the interconnect.

公开(公告)号：US20190221734A1

公开(公告)日：2019-07-18

申请号：US16327603

申请日：2016-09-30

Applicant: INTEL CORPORATION

Inventor： Kaan Oguz ,  Kevin P. O'Brien ,  Brian S. Doyle ,  Mark L. Doczy ,  Charles C. Kuo ,  Daniel G. Ouellette ,  Christopher J. Wiegand ,  MD Tofizur Rahman ,  Brian Maertz

IPC: H01L43/08 ,  H01L43/10 ,  H01L43/12 ,  H01L27/22

CPC classification number: H01L43/08 ,  H01L27/228 ,  H01L43/10 ,  H01L43/12

Abstract: Systems, apparatus, and methods for magnetoresitive memory are described. An apparatus for magnetoresitive memory includes a fixed layer, a free layer, and a tunneling barrier between the fixed layer and the free layer. The free layer is a new alloy consisting of a composition of Cobalt (Co), Iron (Fe), and Boron (B) intermixed with a non-magnetic metal according to a ratio. A thin insert layer of CoFeB may optionally be added between the alloy and the tunneling barrier.

公开(公告)号：US20180248114A1

公开(公告)日：2018-08-30

申请号：US15755444

申请日：2015-09-25

Applicant: Intel Corporation

Inventor： Kaan Oguz ,  Kevin P. O'Brien ,  Christopher J. Wiegand ,  MD Tofizur Rahman ,  Brian S. Doyle ,  Mark L. Doczy ,  Oleg Golonzka ,  Tahir Ghani ,  Justin S. Brockman

IPC: H01L43/08 ,  H01L43/02 ,  H01F10/32 ,  H01L43/10 ,  H01L27/22 ,  G11C11/16 ,  H01L43/12 ,  H01F41/30

Abstract: MTJ material stacks, pSTTM devices employing such stacks, and computing platforms employing such STTM devices. In some embodiments, perpendicular MTJ material stacks with free magnetic layers are magnetically coupled through a metal material layer for improved stability and low damping. In some advantageous embodiments, layers of a free magnetic material stack are magnetically coupled through a coupling layer of a metal comprising at least molybdenum (Mo). The Mo may be in pure form or alloyed with other constituents.

公开(公告)号：US10020232B2

公开(公告)日：2018-07-10

申请号：US15221515

申请日：2016-07-27

Applicant: Intel Corporation

Inventor： Srijit Mukherjee ,  Christopher J. Wiegand ,  Tyler J. Weeks ,  Mark Y. Liu ,  Michael L. Hattendorf

IPC: H01L27/088 ,  H01L21/8238 ,  H01L29/66 ,  H01L27/11 ,  H01L21/8234 ,  H01L27/092 ,  H01L21/28 ,  H01L29/49

CPC classification number: H01L21/82385 ,  H01L21/28008 ,  H01L21/823431 ,  H01L21/823456 ,  H01L21/823821 ,  H01L27/088 ,  H01L27/0886 ,  H01L27/0924 ,  H01L27/1104 ,  H01L29/495 ,  H01L29/66477

Abstract: Integrated circuits including MOSFETs with selectively recessed gate electrodes. Transistors having recessed gate electrodes with reduced capacitive coupling area to adjacent source and drain contact metallization are provided alongside transistors with gate electrodes that are non-recessed and have greater z-height. In embodiments, analog circuits employ transistors with gate electrodes of a given z-height while logic gates employ transistors with recessed gate electrodes of lesser z-height. In embodiments, subsets of substantially planar gate electrodes are selectively etched back to differentiate a height of the gate electrode based on a given transistor's application within a circuit.