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    On-Die Aging Measurements for Dynamic Timing Modeling
    35.
    发明申请
    On-Die Aging Measurements for Dynamic Timing Modeling 审中-公开

    公开(公告)号：US20190146028A1

    公开(公告)日：2019-05-16

    申请号：US16232023

    申请日：2018-12-25

    Applicant: Intel Corporation

    Inventor： Dheeraj Subbareddy ,  Ankireddy Nalamalpu ,  Mahesh A. Iyer ,  Dhananjay Raghavan

    IPC: G01R31/26 ,  G01R31/317 ,  G01R31/28 ,  G01R31/3193

    Abstract: A method includes mapping an AMC into the core fabric of an FPGA and operating the AMC for a select time period. During the select period of time, the AMC counts transition of a signal propagating through the AMC. Timing information based on the counted transitions is stored in a timing model in a memory. The timing information represents an aging characteristic of the core fabric at a time that the AMC is operated. An EDA toolchain uses the timing information in the timing model to generate a timing guard-band for the configurable IC die. The AMC is removed from the core fabric and another circuit device is mapped and fitted into the core fabric using the generated timing guard-band models. The circuit device is operated in the configurable IC die based on the timing guard-band models.

    Apparatus to Synchronize Clocks of Configurable Integrated Circuit Dies Through an Interconnect Bridge
    37.
    发明申请
    Apparatus to Synchronize Clocks of Configurable Integrated Circuit Dies Through an Interconnect Bridge 审中-公开

    公开(公告)号：US20190044520A1

    公开(公告)日：2019-02-07

    申请号：US16024242

    申请日：2018-06-29

    Applicant: Intel Corporation

    Inventor： Lai Guan Tang ,  Ankireddy Nalamalpu ,  Dheeraj Subbareddy

    IPC: H03L7/07 ,  H03L7/087 ,  H03L7/093 ,  H03L7/099 ,  H01L25/065 ,  H01L23/538 ,  G06F1/12

    Abstract: An IC, operable at a first clock phase, includes first and second IOs and a PLL. The PLL includes a control circuit, an input to receive a first clock signal, an output to output a second clock signal, and a first detector to generate a first phase difference signal from the first and second clock signals. The IC includes a second phase detector that is coupled to the PLL's output to receive the second clock signal and is coupled to the first IO to receive a third clock single from a second IC, which is operable at a second clock phase. The second detector generates a second phase difference signal from the second and third clock signals. If the PLL uses the second phase difference signal to generate the second clock signal, then the second clock signal is synchronized with the third clock signal for synchronous data transfer.

    METHODS FOR HANDLING INTEGRATED CIRCUIT DIES WITH DEFECTS
    38.
    发明申请
    METHODS FOR HANDLING INTEGRATED CIRCUIT DIES WITH DEFECTS 审中-公开

    公开(公告)号：US20190044518A1

    公开(公告)日：2019-02-07

    申请号：US16019297

    申请日：2018-06-26

    Applicant: Intel Corporation

    Inventor： Dheeraj Subbareddy ,  Ankireddy Nalamalpu ,  Mahesh A. Iyer

    IPC: H03K19/177 ,  G06F17/50

    Abstract: A method of handling integrated circuit dies with defects is provided. After forming a plurality of dies on one or more silicon wafers, test equipment may be used to identify defects on the dies and to create corresponding defect maps. The defect maps can be combined to form an aggregate defect map. Circuit design tools may create keep-out zones from the aggregate defect map and run learning experiments on each die, while respecting the keep-out zones, to compute design metrics. The circuit design tools may further create larger keep-out zones and run additional learning experiments on each die while respecting the larger keep-out zones to compute additional design metrics. The dies can be binned into different Stock Keeping Units (SKUs) based on one or more of the computed design metrics. Circuit design tools automatically respect the keep-out regions for these dies to program them correctly in the field.

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