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公开(公告)号：US09825649B1
公开(公告)日：2017-11-21
申请号：US15280827
申请日：2016-09-29
Applicant: INTEL CORPORATION
Inventor： Sudhir K. Satpathy , Sanu K. Mathew , Vikram B. Suresh
CPC classification number: H03M7/4006 , H03M7/3086 , H03M7/40 , H03M7/4037
Abstract: An apparatus including a Huffman decoder circuit is described. In a first embodiment, the Huffman decoder circuit includes a register file with simultaneous parallel load capability. The register file is to keep multiple copies of same decoded values in different entries of the register file. The different entries are to be addressed by respective addresses having a same leading edge encoded symbol. The parallel load capability is to simultaneously load a same decoded value for those register file addresses having a same leading edge encoded symbol. In a second embodiment, the Huffman decoder circuit includes a CAM circuit coupled to a register file, wherein respective match lines of the CAM circuit are coupled to respective entries of the register file. The CAM circuit is to keep encoded symbols. The register file is to keep decoded values of the encoded symbols.
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公开(公告)号：US20170111180A1
公开(公告)日：2017-04-20
申请号：US15335158
申请日：2016-10-26
Applicant: Intel Corporation
Inventor： Sanu K. Mathew , Sudhir K. Satpathy
IPC: H04L9/32 , H03K19/177
CPC classification number: H04L9/3278 , G06Q10/08 , G09C1/00 , H03K19/17768 , H04L2209/04 , H04L2209/12
Abstract: Embodiments include apparatuses, methods, and systems for a physically unclonable function (PUF) circuit. The PUF circuit may include an array of PUF cells to generate respective PUF bits of an encryption code. Individual PUF cells may include first and second inverters cross-coupled between a bit node and a bit bar node. The individual PUF cells may further include a first pre-charge transistor coupled to the bit node and configured to receive a clock signal via a first clock path, and a second pre-charge transistor coupled to the bit bar node and configured to receive the clock signal via a second clock path. Features and techniques of the PUF cells are disclosed to improve the stability and/or bias strength of the PUF cells, to generate a dark bit mask for the array of PUF cells, and to improve resilience to probing attacks. Other embodiments may be described and claimed.
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公开(公告)号：US20170090872A1
公开(公告)日：2017-03-30
申请号：US14865009
申请日：2015-09-25
Applicant: Intel Corporation
Inventor： Sanu K. Mathew , David Johnston , Sudhir K. Satpathy
IPC: G06F7/58
CPC classification number: G06F7/588 , G06F7/483 , G06F2207/58 , H04L9/0637 , H04L9/0869
Abstract: A processor includes an execution unit to generate a random number. The execution unit includes entropy source circuits, correlation circuits, and an extractor circuit. The entropy source circuits include all-digital components and are to generate an initial randomized bit stream. The correlation circuits are to remove correlations from the initial randomized bit stream to yield an intermediate randomized bit stream. The extractor circuit is to select a subset of the intermediate randomized bit stream as a random output of the execution unit.
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34.发明申请SMS4 ACCELERATION PROCESSORS HAVING ENCRYPTION AND DECRYPTION MAPPED ON A SAME HARDWARE 有权SMS4加密处理器在同一硬件上映射加密和解密公开(公告)号：US20160379014A1
公开(公告)日：2016-12-29
申请号：US14751995
申请日：2015-06-26
Applicant: Intel Corporation
Inventor： Sudhir K. Satpathy , Sanu K. Mathew , Kirk S. Yap , Vinodh Gopal
CPC classification number: G06F21/74 , G06F21/73 , G06F2221/2107 , G09C1/00 , H04L9/0631 , H04L2209/122
Abstract: A processing system includes a processing core and a hardware accelerator communicatively coupled to the processing core. The hardware accelerator includes a data register having a plurality of data bits and a key register having a plurality of key bits. The hardware accelerator also includes a data mode selector module to select one of an encrypt mode or a decrypt mode for processing the plurality of data bits. The hardware accelerator further includes a key mode selector module to select one of the encrypt mode or the decrypt mode for processing the plurality of key bits.
Abstract translation: 处理系统包括处理核心和通信地耦合到处理核心的硬件加速器。 硬件加速器包括具有多个数据位的数据寄存器和具有多个键位的键寄存器。 硬件加速器还包括数据模式选择器模块，用于选择处理多个数据位的加密模式或解密模式之一。 硬件加速器还包括密钥模式选择器模块，用于选择用于处理多个密钥位的加密模式或解密模式之一。
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公开(公告)号：US11258459B2
公开(公告)日：2022-02-22
申请号：US16996012
申请日：2020-08-18
Applicant: Intel Corporation
Inventor： Vinodh Gopal , James D. Guilford , Sudhir K. Satpathy , Sanu K. Mathew
Abstract: Methods and apparatus to parallelize data decompression are disclosed. An example method selecting initial starting positions in a compressed data bitstream; adjusting a first one of the initial starting positions to determine a first adjusted starting position by decoding the bitstream starting at a training position in the bitstream, the decoding including traversing the bitstream from the training position as though first data located at the training position is a valid token; outputting first decoded data generated by decoding a first segment of the bitstream starting from the first adjusted starting position; and merging the first decoded data with second decoded data generated by decoding a second segment of the bitstream, the decoding of the second segment starting from a second position in the bitstream and being performed in parallel with the decoding of the first segment, and the second segment preceding the first segment in the bitstream.
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Patent Agency Ranking
公开(公告)号：US10694217B2
公开(公告)日：2020-06-23
申请号：US16137985
申请日：2018-09-21
Applicant: Intel Corporation
Inventor： Sudhir K. Satpathy , Vinodh Gopal , James D. Guilford , Sanu K. Mathew , Vikram B. Suresh
Abstract: A processing device includes compression circuitry to encode an input stream with an encoding that translates multiple symbols of fixed length into multiple codes of variable length between one and a maximum length, to generate a compressed stream. The compression circuitry is to: determine at least a first symbol of the multiple symbols having a first code that exceeds the maximum length; identify a short code of the multiple codes that is to be lengthened to provide an increased encoding capacity for the at least the first symbol; generate multiple code-length converted values including to increase the length of the short code to the maximum length and decrease, to the maximum length, a length of the first code of the at least the first symbol; and generate, with use of the set of code-length converted values, the compressed stream at the output terminal.
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公开(公告)号：US10606765B2
公开(公告)日：2020-03-31
申请号：US15873729
申请日：2018-01-17
Applicant: Intel Corporation
Inventor： Sudhir K. Satpathy , Sanu K. Mathew , Vikram B. Suresh
Abstract: A cryptographic hardware accelerator identifies a mapped input bit sequence by applying a mapping transformation to an input bit sequence retrieved from memory and represented by a first element of a finite-prime field. The mapped input bit sequence is represented by a first element of a composite field. The accelerator identifies a mapped first key by applying the mapping transformation to an input key represented by a second element of the finite-prime field. The mapped first key is represented by the second element. The accelerator performs, within the composite field, a cryptographic round on the mapped input bit sequence using the mapped first key during a first round of the at least one cryptographic round, to generate a processed bit sequence. The accelerator identifies an output bit sequence to be stored back in the finite-prime field by applying an inverse mapping transformation to the processed bit sequence.
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公开(公告)号：US10579335B2
公开(公告)日：2020-03-03
申请号：US15627526
申请日：2017-06-20
Applicant: Intel Corporation
Inventor： Sudhir K. Satpathy , Sanu K. Mathew , Vikram B. Suresh , Raghavan Kumar
Abstract: In one embodiment, an apparatus comprises a multiplier circuit to: identify a plurality of partial products associated with a multiply operation; partition the plurality of partial products into a first set of partial products, a second set of partial products, and a third set of partial products; determine whether the multiply operation is associated with a square operation; upon a determination that the multiply operation is associated with the square operation, compute a result based on the first set of partial products and the third set of partial products; and upon a determination that the multiply operation is not associated with the square operation, compute the result based on the first set of partial products, the second set of partial products, and the third set of partial products.
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公开(公告)号：US20190245679A1
公开(公告)日：2019-08-08
申请号：US15887290
申请日：2018-02-02
Applicant: Intel Corporation
Inventor： Vikram B. Suresh , Sanu K. Matthew , Sudhir K. Satpathy , Vinodh Gopal
Abstract: Modifications to Advanced Encryption Standard (AES) hardware acceleration circuitry are described to allow hardware acceleration of the key operations of any non-AES block cipher, such as SMT and Camellia. In some embodiments the GF(28) inverse computation circuit in the AES S-box is used to compute X−1 (where X is the input plaintext or ciphertext byte), and hardware support is added to compute parallel GF(28) matrix multiplications. The embodiments described herein have minimal hardware overhead while achieving greater speed than software implementations.
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公开(公告)号：US20190205093A1
公开(公告)日：2019-07-04
申请号：US15857281
申请日：2017-12-28
Applicant: Intel Corporation
Inventor： Vikram B. Suresh , Sanu K. Mathew , Sudhir K. Satpathy , Vinodh Gopal
Abstract: In one embodiment, a processor comprises a multiplier circuit to operate in an integer multiplication mode responsive to a first value of a configuration parameter; and operate in a carry-less multiplication mode responsive to a second value of the configuration parameter.
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