公开(公告)号：US11742284B2

公开(公告)日：2023-08-29

申请号：US17053144

申请日：2018-12-12

Applicant: Intel Corporation

Inventor： Zhicheng Ding ,  Bin Liu ,  Yong She ,  Zhijun Xu

IPC: H01L23/525 ,  H01L25/065 ,  H01L23/00

CPC classification number: H01L23/525 ,  H01L24/48 ,  H01L25/0657 ,  H01L2924/15311

Abstract: Embodiments described herein provide techniques of forming an interconnect structure using lithographic and deposition processes. The interconnect structure can be used to couple components of a semiconductor package. For one example, a semiconductor package includes a die stack and an interconnect structure formed on the die stack. The die stack comprises a plurality of dies. Each die in the die stack comprises: a first surface; a second surface opposite the first surface; sidewall surfaces coupling the first surface to the second surface; and a pad on the first surface. A one sidewall surface of one of the dies has a sloped profile. The semiconductor package also includes an interconnect structure positioned on the first surfaces and the sidewall with the sloped profile. In this semiconductor package, the interconnect structure electrically couples the pad on each of the dies to each other.

公开(公告)号：US11081451B2

公开(公告)日：2021-08-03

申请号：US16492323

申请日：2017-03-10

Applicant: Intel Corporation

Inventor： Yong She ,  Bin Liu ,  Zhicheng Ding ,  Aiping Tan

IPC: H01L23/00 ,  H01L23/498 ,  H01L25/065 ,  H01L27/1157 ,  G11C5/04 ,  H01L27/11524

Abstract: A microelectronic device can include a polymer, a semiconductor, and a matching layer. The polymer can include a first coefficient of thermal expansion. The semiconductor can be coupled to the polymer layer. The matching layer can be adjacent the semiconductor, and the matching layer can include a second coefficient of thermal expansion that is about the same as the first coefficient of thermal expansion.

公开(公告)号：US10930622B2

公开(公告)日：2021-02-23

申请号：US16940070

申请日：2020-07-27

Applicant: Intel Corporation

Inventor： Zhicheng Ding ,  Bin Liu ,  Yong She ,  Aiping Tan ,  Li Deng

IPC: H01L25/065 ,  H01L25/18 ,  H01L25/00 ,  H01L21/66 ,  G01R31/28

Abstract: A pre-packaged stair-stacked memory module is mounted on a board with at least one additional component. A stair-stacked memory module includes a plurality of memory dice that are stacked vertically with respect to a processor die. A spacer is used adjacent to the processor die to create a bridge for the stair-stacked memory module. Each memory die in the stair-stacked memory module includes a vertical bond wire that emerges from a matrix for connection. The matrix encloses the stair-stacked memory module and at least a portion of the processor die. The matrix might also enclose the at least one additional component.

公开(公告)号：US20200227387A1

公开(公告)日：2020-07-16

申请号：US16641221

申请日：2017-09-29

Applicant: INTEL CORPORATION

Inventor： Zhijun Xu ,  Bin Liu ,  Yong She ,  Zhicheng Ding

IPC: H01L25/065 ,  H01L25/18 ,  H01L23/00 ,  H01L25/00

Abstract: An apparatus comprising: a die stack comprising at least one die pair, the at least one die pair having a first die over a second die, the first die and the second die both having a first surface and a second surface, the second surface of the first die over the first surface of the second die; and an adhesive film between the first die and the second die of the at least one die pair; wherein the adhesive film comprises an insulating layer and a conductive layer, the insulating layer adhering to the second surface of the first die and the conductive layer adhering to the first surface of the second die.

公开(公告)号：US10396055B2

公开(公告)日：2019-08-27

申请号：US15749760

申请日：2015-09-25

Applicant: Intel Corporation

Inventor： Yong She ,  John G. Meyers ,  Zhicheng Ding ,  Richard Patten

IPC: H01L23/48 ,  H01L25/065 ,  H01L23/488 ,  H01L23/00 ,  H01L23/49 ,  H01L23/50 ,  H01L25/00 ,  H01L23/538

Abstract: Techniques and mechanisms for interconnecting stacked integrated circuit (IC) dies. In an embodiment, a first end of a wire is coupled to a first IC die of a stack, where a second end of the wire is further anchored to the stack independent of the coupled first end. A package material is subsequently disposed around IC dies of the stack and a first portion of the wire that includes the first end. Two-point anchoring of the wire to the stack aids in providing mechanical support to resist movement that might otherwise displace and/or deform the wire while the package material is deposited. In another embodiment, the first portion of the wire is separated from the rest of the wire, and a redistribution layer is coupled to the first portion to enable interconnection between the first IC die and another IC die of the stack.

公开(公告)号：US20190214370A1

公开(公告)日：2019-07-11

申请号：US16326330

申请日：2016-09-30

Applicant: Intel Corporation

Inventor： Zhicheng Ding ,  Bin Liu ,  Yong She ,  Aiping Tan ,  Li Deng

IPC: H01L25/065 ,  H01L25/18 ,  H01L21/66 ,  H01L25/00

Abstract: A system in package includes a stair-stacked memory module that is stacked vertically with respect to a processor die. A spacer is used adjacent to the processor die to create a bridge for the stair-stacked memory module. Each memory die in the stair-stacked memory module includes a vertical bond wire that emerges from a matrix for connection. The matrix encloses the stair-stacked memory module and at least a portion of the processor die.