公开(公告)号：US20190312064A1

公开(公告)日：2019-10-10

申请号：US16447000

申请日：2019-06-20

Applicant: Japan Display Inc.

Inventor： Toshinari SASAKI ,  Hajime Watakabe ,  Akihiro Hanada ,  Marina Shiokawa

IPC: H01L27/12 ,  H01L29/786

Abstract: A semiconductor device includes a oxide semiconductor layer, a gate electrode arranged above the oxide semiconductor layer, a gate insulation layer between the oxide semiconductor layer and the gate electrode, a first insulation layer arranged above the oxide semiconductor layer and arranged with a first aperture part, wiring including an aluminum layer arranged above the first insulation layer, the wiring being electrically connected to the oxide semiconductor layer via the first aperture part, a barrier layer including aluminum oxide above the first insulation layer, above the wiring and covering a side surface of the wiring, and an organic insulation layer arranged above the barrier layer.

公开(公告)号：US10211235B2

公开(公告)日：2019-02-19

申请号：US15678501

申请日：2017-08-16

Applicant: Japan Display Inc.

Inventor： Isao Suzumura ,  Hajime Watakabe ,  Akihiro Hanada ,  Hirokazu Watanabe

IPC: H01L27/12 ,  H01L21/02 ,  H01L29/423 ,  H01L29/66 ,  H01L29/786 ,  G03F7/00 ,  G02F1/1343 ,  G02F1/1362 ,  G02F1/1368 ,  H01L27/32

Abstract: The purpose of the present invention is to form both LTPS TFT and Ply-Si TFT on a same substrate. The feature of the display device to realize the above purpose is that: a display device comprising: a substrate including a first TFT having an oxide semiconductor layer and a second TFT having a Poly-Si layer, an undercoat is formed on the substrate, the oxide semiconductor layer is formed on or above the undercoat, a first interlayer insulating film is formed on or above the oxide semiconductor layer, the Poly-Si layer is formed on or above the first interlayer insulating film.

公开(公告)号：US10177174B2

公开(公告)日：2019-01-08

申请号：US15617547

申请日：2017-06-08

Applicant: Japan Display Inc.

Inventor： Akihiro Hanada ,  Masayoshi Fuchi

IPC: H01L27/12 ,  H01L21/02 ,  H01L21/768 ,  H01L23/522 ,  H01L23/532 ,  H01L29/786

Abstract: According to one embodiment, a semiconductor device includes an insulating substrate, a first semiconductor layer located above the insulating substrate, a second semiconductor layer located above the insulating substrate, an insulating layer which covers the first semiconductor layer and the second semiconductor layer, and includes a first contact hole reaching the first semiconductor layer and a second contact hole reaching the second semiconductor layer, a barrier layer which covers one of the first semiconductor layer inside the first contact hole and the second semiconductor layer inside the second contact hole, and a first conductive layer which is in contact with the barrier layer.

公开(公告)号：US10115740B2

公开(公告)日：2018-10-30

申请号：US15405511

申请日：2017-01-13

Applicant: Japan Display Inc.

Inventor： Akihiro Hanada ,  Hajime Watakabe ,  Kazufumi Watabe

IPC: H01L29/12 ,  H01L29/40 ,  H01L23/48 ,  H01L27/12 ,  H01L29/423 ,  H01L29/51 ,  H01L29/786

Abstract: According to one embodiment, a semiconductor device includes an insulating substrate, a first semiconductor layer formed of silicon and positioned above the insulating substrate, a second semiconductor layer formed of a metal oxide and positioned above the first semiconductor layer, a first insulating film formed of a silicon nitride and positioned between the first semiconductor layer and the second semiconductor layer, and a block layer positioned between the first semiconductor film and the second semiconductor layer, the block layer hydrogen diffusion of which is lower than that of the first insulating film.

公开(公告)号：US20160149047A1

公开(公告)日：2016-05-26

申请号：US14944711

申请日：2015-11-18

Applicant: Japan Display Inc.

Inventor： Hajime Watakabe ,  Arichika Ishida ,  Takashi Okada ,  Masayoshi Fuchi ,  Akihiro Hanada

IPC: H01L29/786 ,  H01L23/00 ,  H01L21/385 ,  H01L29/66

CPC classification number: H01L29/7869 ,  H01L29/42384 ,  H01L29/4908 ,  H01L29/66969 ,  H01L29/78603 ,  H01L29/78606

Abstract: According to one embodiment, a thin-film transistor and a method of manufacturing the same achieve size reduction of the thin-film transistor while using an oxide semiconductor layer. The oxide semiconductor layer includes a channel region, a source region, and a drain region. A gate electrode is arranged at a position spaced from the channel region of the oxide semiconductor layer so as to face the channel region. A source electrode is electrically connected to the source region of the oxide semiconductor layer. A drain electrode is electrically connected to the drain region of the oxide semiconductor layer. An undercoat layer adjoins the source region and the drain region of the oxide semiconductor layer. A hydrogen blocking layer has a hydrogen concentration lower than that in the undercoat layer and separates the undercoat layer and the channel region of the oxide semiconductor layer.

Abstract translation: 根据一个实施例，薄膜晶体管及其制造方法在使用氧化物半导体层时实现薄膜晶体管的尺寸减小。 氧化物半导体层包括沟道区，源极区和漏极区。 栅电极配置在与氧化物半导体层的沟道区隔开的位置，以面对沟道区。 源极电极与氧化物半导体层的源极区电连接。 漏电极与氧化物半导体层的漏区电连接。 底涂层邻接氧化物半导体层的源极区和漏极区。 氢阻挡层的氢浓度低于底涂层中的氢浓度，并分离底涂层和氧化物半导体层的沟道区。

公开(公告)号：US12213351B2

公开(公告)日：2025-01-28

申请号：US17570396

申请日：2022-01-07

Applicant: Japan Display Inc.

Inventor： Akihiro Hanada ,  Toshinari Sasaki ,  Ryo Onodera

IPC: H10K59/124 ,  H10K59/121

Abstract: According to one embodiment, in a first concentration of an impurity element contained in a first impurity region, a second concentration of the impurity element contained in a second impurity region, a third concentration of the impurity element contained in a third impurity region, and a fourth concentration of the impurity element contained in a high-concentration impurity region, the third concentration is equal to the fourth concentration, the third concentration is higher than the first concentration, and the first concentration is higher than the second concentration.

公开(公告)号：US12191398B2

公开(公告)日：2025-01-07

申请号：US17579740

申请日：2022-01-20

Applicant: Japan Display Inc.

Inventor： Akihiro Hanada ,  Takuo Kaitoh ,  Masashi Tsubuku

IPC: H01L29/78 ,  H01L29/786

Abstract: The purpose of the present invention is to suppress a variation in a threshold voltage (Δ Vth) in a Thin Film Transistor (TFT) using an oxide semiconductor. The present invention takes a structure as follows to attain this purpose. A semiconductor device having TFT using an oxide semiconductor including: a channel region, a source region, a drain region, and a transition region between the channel region and the source region and between the channel region and the drain region, in which a resistivity of the transition region is smaller than that of the channel region, and larger than that of the source region or the drain region; a source electrode is formed overlapping the source region, and a drain electrode is formed overlapping the drain region; and a thickness of the transition region of the oxide semiconductor is larger than a thickness of the channel region of the oxide semiconductor.

公开(公告)号：US12181759B2

公开(公告)日：2024-12-31

申请号：US18457350

申请日：2023-08-29

Applicant: Japan Display Inc.

Inventor： Akihiro Hanada ,  Hitoshi Tanaka

IPC: G02F1/1362

Abstract: According to one embodiment, a display device includes a transparent semiconductor, a first insulating layer, a gate electrode, a second insulating layer, a source electrode, a third insulating layer, a transparent electrode which is in contact with the semiconductor in a second contact hole penetrating the first insulating layer, the second insulating layer and the third insulating layer, a fourth insulating layer, a color filter, and a pixel electrode electrically connected to the transparent electrode. The first insulating layer and the second insulating layer are silicon oxide layers. At least one of the third insulating layer and the fourth insulating layer is a silicon nitride layer.

公开(公告)号：US12176438B2

公开(公告)日：2024-12-24

申请号：US17549882

申请日：2021-12-14

Applicant: Japan Display Inc.

Inventor： Hajime Watakabe ,  Kentaro Miura ,  Toshinari Sasaki ,  Takeshi Sakai ,  Akihiro Hanada ,  Masashi Tsubuku

IPC: H01L29/78 ,  H01L29/423 ,  H01L29/786

Abstract: According to one embodiment, a semiconductor device includes an oxide semiconductor. The oxide semiconductor includes a first edge portion and a second edge portion intersecting a gate electrode, a first area overlapping the gate electrode, a second area along the first edge portion, a third area along the second edge portion, a fourth area the first edge portion, a fifth area along the second edge portion, a sixth area surrounded by the first area, the second area and the third area, and a seventh area surrounded by the first area, the fourth area and the fifth area. The first area, the second area and the third area, the fourth area and the fifth area have a higher resistivity than those of the sixth area and the seventh area.

公开(公告)号：US12166131B2

公开(公告)日：2024-12-10

申请号：US18328788

申请日：2023-06-05

Applicant: Japan Display Inc.

Inventor： Hajime Watakabe ,  Tomoyuki Ito ,  Toshihide Jinnai ,  Isao Suzumura ,  Akihiro Hanada ,  Ryo Onodera

IPC: H01L27/12 ,  H01L21/02 ,  H01L21/426 ,  H01L21/4757 ,  H01L21/4763 ,  H01L29/24 ,  H01L29/423 ,  H01L29/49 ,  H01L29/66 ,  H01L29/786 ,  G02F1/1368

Abstract: A semiconductor device includes thin film transistors each having an oxide semiconductor. The oxide semiconductor has a channel region, a drain region, a source region, and low concentration regions which are lower in impurity concentration than the drain region and the source region. The low concentration regions are located between the channel region and the drain region, and between the channel region and the source region. Each of the thin film transistors has a gate insulating film on the channel region and the low concentration regions, an aluminum oxide film on a first part of the gate insulating film, the first part being located on the channel region, and a gate electrode on the aluminum oxide film and a second part of the gate insulating film, the second part being located on the low concentration regions.