公开(公告)号：US08670102B2

公开(公告)日：2014-03-11

申请号：US13005538

申请日：2011-01-13

Applicant: Mien-Mien Cheng ,  Yi-Suei Liao ,  Jian-Hong Lin ,  Chien-Feng Chiu

Inventor： Mien-Mien Cheng ,  Yi-Suei Liao ,  Jian-Hong Lin ,  Chien-Feng Chiu

IPC: G02F1/1333

CPC classification number: G02F1/136259 ,  G02F2001/13606 ,  G02F2001/136263 ,  G02F2001/136272

Abstract: A display panel includes an active device array substrate, an opposite substrate, and a liquid crystal layer. The active device array substrate includes a substrate and further includes a pixel array, signal lines, and first and second repairing lines all disposed on the substrate. The signal lines electrically connect the pixel array. The first repairing line includes first and second line segments respectively located on first and second sides of the pixel array. The first side is substantially perpendicular to the second side. The first and second line segments are electrically connected. The second repairing line includes third and fourth line segments respectively located on third and second sides of the pixel array. The third side is substantially parallel to the first side. The fourth and third line segments are electrically connected. The opposite substrate above the active device array substrate does not cover the first and third line segments.

Abstract translation: 显示面板包括有源器件阵列衬底，相对衬底和液晶层。 有源器件阵列衬底包括衬底，并且还包括像素阵列，信号线以及全部设置在衬底上的第一和第二修复线。 信号线电连接像素阵列。 第一修复线包括分别位于像素阵列的第一和第二侧上的第一和第二线段。 第一侧基本垂直于第二侧。 第一和第二线段电连接。 第二修复线包括分别位于像素阵列的第三和第二侧上的第三和第四线段。 第三侧基本上平行于第一侧。 第四和第三线段电连接。 有源器件阵列衬底上方的相对衬底不覆盖第一和第三线段。

公开(公告)号：US08648592B2

公开(公告)日：2014-02-11

申请号：US13231812

申请日：2011-09-13

Applicant: Bi-Ling Lin ,  Jian-Hong Lin ,  Ming-Hong Hsieh ,  Lee-Der Chen ,  Jiaw-Ren Shih ,  Chwei-Ching Chiu

Inventor： Bi-Ling Lin ,  Jian-Hong Lin ,  Ming-Hong Hsieh ,  Lee-Der Chen ,  Jiaw-Ren Shih ,  Chwei-Ching Chiu

IPC: G01V3/00

CPC classification number: H01L23/5256 ,  G01R31/2853 ,  G01R31/2858 ,  G01R31/2884 ,  H01L22/34 ,  H01L23/522 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Semiconductor device components and methods are disclosed. In one embodiment, a semiconductor device component includes a conductive segment having a first surface, a second surface opposite the first surface, a first end, and a second end opposite the first end. A first via is coupled to the second surface of the conductive segment at the first end. A second via is coupled to the first surface of the conductive segment at the second end, and a third via is coupled to the second surface of the conductive segment at the second end.

Abstract translation: 公开了半导体器件组件和方法。 在一个实施例中，半导体器件部件包括具有第一表面，与第一表面相对的第二表面，第一端和与第一端相对的第二端的导电段。 第一通孔在第一端耦合到导电段的第二表面。 第二通孔在第二端处耦合到导电段的第一表面，并且第三通孔在第二端耦合到导电段的第二表面。

公开(公告)号：US08541264B2

公开(公告)日：2013-09-24

申请号：US13548039

申请日：2012-07-12

Applicant: Jian-Hong Lin ,  Kang-Cheng Lin ,  Tzu-Li Lee

Inventor： Jian-Hong Lin ,  Kang-Cheng Lin ,  Tzu-Li Lee

IPC: H01L21/82

CPC classification number: H01L23/5258 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method for forming a semiconductor structure is provided to prevent energy that is used to blow at least one fuse formed on a metal layer above a semiconductor substrate from causing damage on the structure. The semiconductor structure includes a device, guard ring, protection ring, and at least one protection layer. The device is constructed on the semiconductor substrate underneath the fuse. A seal ring, which surrounds the fuse, is constructed on at least one metal layer between the device and the fuse for confining the energy therein. The protection layer is formed within the seal ring, on at least one metal layer between the device and the fuse for shielding the device from being directly exposed to the energy.

Abstract translation: 提供一种用于形成半导体结构的方法，以防止用于吹送形成在半导体衬底上的金属层上的至少一个熔丝的能量引起对结构的损坏。 半导体结构包括器件，保护环，保护环和至少一个保护层。 该器件构造在保险丝下方的半导体衬底上。 围绕熔丝的密封环构造在设备和保险丝之间的至少一个金属层上，以将能量限制在其中。 保护层形成在密封环内，在设备和保险丝之间的至少一个金属层上，用于屏蔽器件不会直接暴露于能量。

公开(公告)号：US20120276732A1

公开(公告)日：2012-11-01

申请号：US13548039

申请日：2012-07-12

Applicant: Jian-Hong Lin ,  Kang-Cheng Lin ,  Tzu-Li Lee

Inventor： Jian-Hong Lin ,  Kang-Cheng Lin ,  Tzu-Li Lee

IPC: H01L21/768

CPC classification number: H01L23/5258 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method for forming a semiconductor structure is provided to prevent energy that is used to blow at least one fuse formed on a metal layer above a semiconductor substrate from causing damage on the structure. The semiconductor structure includes a device, guard ring, protection ring, and at least one protection layer. The device is constructed on the semiconductor substrate underneath the fuse. A seal ring, which surrounds the fuse, is constructed on at least one metal layer between the device and the fuse for confining the energy therein. The protection layer is formed within the seal ring, on at least one metal layer between the device and the fuse for shielding the device from being directly exposed to the energy.

Abstract translation: 提供一种用于形成半导体结构的方法，以防止用于吹送形成在半导体衬底上的金属层上的至少一个熔丝的能量引起对结构的损坏。 半导体结构包括器件，保护环，保护环和至少一个保护层。 该器件构造在保险丝下方的半导体衬底上。 围绕熔丝的密封环构造在设备和保险丝之间的至少一个金属层上，以将能量限制在其中。 保护层形成在密封环内，在设备和保险丝之间的至少一个金属层上，用于屏蔽器件不会直接暴露于能量。

公开(公告)号：US20120268434A1

公开(公告)日：2012-10-25

申请号：US13471425

申请日：2012-05-14

Applicant: Jian-Hong Lin

Inventor： Jian-Hong Lin

IPC: G06F3/038 ,  G02F1/1333

CPC classification number: G02F1/1345 ,  G02F1/136259 ,  G02F2001/136272

Abstract: A display panel including a first substrate, a second substrate, and a liquid crystal layer. The first substrate comprises a display region and a peripheral circuit region adjacent to the display region, and the first substrate includes a pixel array, a plurality of test shorting bars, and a plurality of wires. The pixel array is disposed in the display region. The test shorting bars are disposed in the peripheral circuit region. The wires are disposed in the peripheral circuit region and electrically connected with the pixel array. Moreover, at least one wire and one of the test shorting bars respectively share a part for connecting with each other and forming a common trace. Additionally, the second substrate is disposed opposite to the first substrate. The liquid crystal layer is disposed between the first substrate and the second substrate.

Abstract translation: 一种显示面板，包括第一基板，第二基板和液晶层。 第一衬底包括与显示区域相邻的显示区域和外围电路区域，并且第一衬底包括像素阵列，多个测试短路条和多条电线。 像素阵列设置在显示区域中。 测试短路棒设置在外围电路区域中。 电线布置在外围电路区域中并与像素阵列电连接。 此外，至少一根线和一个测试短路棒分别共享用于彼此连接并形成公共痕迹的部分。 另外，第二基板与第一基板相对设置。 液晶层设置在第一基板和第二基板之间。

公开(公告)号：US08212330B2

公开(公告)日：2012-07-03

申请号：US12879770

申请日：2010-09-10

Applicant: Hsien-Wei Chen ,  Jian-Hong Lin ,  Tzu-Li Lee

Inventor： Hsien-Wei Chen ,  Jian-Hong Lin ,  Tzu-Li Lee

IPC: H01L23/52

CPC classification number: H01L21/7682 ,  H01L21/76828 ,  H01L21/76829 ,  H01L2221/1047

Abstract: An interconnect structure of an integrated circuit having improved reliability and a method for forming the same are provided. The method includes providing a substrate, forming a dielectric layer overlying the substrate, performing a first shrinking process, wherein the dielectric layer shrinks and has a first shrinkage rate, forming a conductive feature in the dielectric layer after the step of performing the first shrinking process, and performing a second shrinking process after the step of forming the conductive feature, wherein the dielectric layer substantially shrinks and has a second shrinkage rate.

Abstract translation: 提供了具有改善的可靠性的集成电路的互连结构及其形成方法。 该方法包括提供衬底，形成覆盖在衬底上的电介质层，执行第一收缩过程，其中电介质层收缩并具有第一收缩率，在执行第一收缩过程的步骤之后在介电层中形成导电特征 并且在形成导电特征的步骤之后执行第二收缩过程，其中介电层基本上收缩并且具有第二收缩率。

公开(公告)号：US08208084B2

公开(公告)日：2012-06-26

申请号：US12369748

申请日：2009-02-12

Applicant: Jian-Hong Lin

Inventor： Jian-Hong Lin

IPC: G02F1/1333 ,  G02F1/13

CPC classification number: G02F1/1345 ,  G02F1/136259 ,  G02F2001/136272

Abstract: An array substrate having a display region and a peripheral circuit region adjacent to the display region is provided. The array substrate includes a pixel array, a plurality of test shorting bars and a plurality of wires. The pixel array is disposed in the display region. The test shorting bars are disposed in the peripheral circuit region. The wires electrically connected with the pixel array are disposed in the peripheral circuit region. Specially, at least one wire and the test shorting bar share a part for connecting each other and the part forms a common trace.

Abstract translation: 提供了具有与显示区域相邻的显示区域和外围电路区域的阵列基板。 阵列基板包括像素阵列，多个测试短路棒和多根线。 像素阵列设置在显示区域中。 测试短路棒设置在外围电路区域中。 与像素阵列电连接的布线设置在外围电路区域中。 特别地，至少一根电线和测试短路棒共享用于彼此连接的部件，并且该部件形成共同的轨迹。

公开(公告)号：US07646207B2

公开(公告)日：2010-01-12

申请号：US11849836

申请日：2007-09-04

Applicant: Jian-Hong Lin ,  Chin Chuan Peng ,  Shou-Chung Lee ,  Chien-Jung Wang ,  Chien Shih Tsai ,  Bi-Ling Lin ,  Yi-Lung Cheng

Inventor： Jian-Hong Lin ,  Chin Chuan Peng ,  Shou-Chung Lee ,  Chien-Jung Wang ,  Chien Shih Tsai ,  Bi-Ling Lin ,  Yi-Lung Cheng

IPC: G01R27/08

CPC classification number: G01R31/2858 ,  G01R31/2853 ,  G01R31/2884 ,  H01L22/14 ,  H01L22/34 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method for measuring a property of interconnections is provided. The method includes the following steps. A plurality of interconnection test patterns are provided. A pad to which the plurality of interconnection test patterns are parallelly connected is formed. At least one resistor is formed between at least one of the plurality of interconnection test patterns and the pad. The property of the plurality of interconnection test patterns is measured by applying a current, a voltage and/or a mechanical stress to the pad.

Abstract translation: 提供了一种用于测量互连性质的方法。 该方法包括以下步骤。 提供多个互连测试图案。 形成多个互连测试图案并联连接的焊盘。 至少一个电阻器形成在所述多个互连测试图案中的至少一个与所述焊盘之间。 通过对焊盘施加电流，电压和/或机械应力来测量多个互连测试图案的性质。

公开(公告)号：US20070158835A1

公开(公告)日：2007-07-12

申请号：US11332566

申请日：2006-01-12

Applicant: Jian-Hong Lin ,  Hsueh-Chung Chen ,  Yi-Lung Cheng ,  Ta-Wei Lee ,  Chih-Tao Lin ,  Jyh-Kang Ting ,  Lee-Chung Lu

Inventor： Jian-Hong Lin ,  Hsueh-Chung Chen ,  Yi-Lung Cheng ,  Ta-Wei Lee ,  Chih-Tao Lin ,  Jyh-Kang Ting ,  Lee-Chung Lu

IPC: H01L23/48

CPC classification number: H01L23/5226 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method is disclosed for determining a size of an interconnect between a first and a second conductor respectively in two layers of an integrated circuit while scaling from a reference processing technology to a predetermined processing technology. The method comprises selecting a set of design rules for the conductors based on the predetermined processing technology, determining a length of a first side of a rectangular cross sectional area of the interconnect based on the design rules and a scaling rule for scaling such a length from the reference processing technology to the predetermined processing technology, and determining a length of a second side of the cross sectional area of the interconnect for compensating an increase of a resistance of the interconnect due to the scaling from the reference processing technology to the predetermined processing technology.

Abstract translation: 公开了一种用于在从参考处理技术缩放到预定处理技术的同时，分别在集成电路的两层中确定第一和第二导体之间的互连尺寸的方法。 该方法包括基于预定的处理技术来选择一组导体的设计规则，基于设计规则确定互连的矩形横截面积的第一侧的长度，以及用于缩放这种长度的缩放规则 将参考处理技术应用于预定处理技术，以及确定互连横截面积的第二侧的长度，以补偿由于从参考处理技术到预定处理技术的缩放而导致的互连电阻的增加 。

公开(公告)号：US07135406B2

公开(公告)日：2006-11-14

申请号：US10983681

申请日：2004-11-09

Applicant: Jian-Hong Lin ,  Ying-Jen Kao ,  Jye-Yen Cheng

Inventor： Jian-Hong Lin ,  Ying-Jen Kao ,  Jye-Yen Cheng

IPC: H01L21/44 ,  H01L21/4763

CPC classification number: H01L21/76808

Abstract: Methods for forming openings in damascene structures, such as dual damascene structures are provided, using plug materials having varied etching rates. In one embodiment, a semiconductor substrate is provided with a low-k material layer formed thereabove, the low-k material layer having an upper surface and at least one via opening formed therethrough. A first plug material layer is formed over the low-k material layer and filled in the via opening, the first plug material layer having a first etching rate. The first plug material layer is etched back to form a first plug partially filling the via opening. A second plug material layer is formed over the low-k material layer and the first plug. The second plug material layer is etched back to form a second plug partially below the upper surface of the low-k material layer, the second plug material layer having a second etching rate higher than the first etching rate.

Abstract translation: 提供了在镶嵌结构中形成开口的方法，例如双镶嵌结构，使用具有不同蚀刻速率的塞子材料。 在一个实施例中，半导体衬底设置有形成在其上的低k材料层，低k材料层具有上表面和至少一个通孔形成。 第一插塞材料层形成在低k材料层上并填充在通孔中，第一插塞材料层具有第一蚀刻速率。 将第一插塞材料层回蚀刻以形成部分填充通孔开口的第一插头。 在低k材料层和第一插塞上形成第二插塞材料层。 第二插塞材料层被回蚀刻以在低k材料层的上表面部分下方形成第二插头，第二插塞材料层具有高于第一蚀刻速率的第二蚀刻速率。