公开(公告)号：US20180006669A1

公开(公告)日：2018-01-04

申请号：US15242605

申请日：2016-08-22

Applicant: PHISON ELECTRONICS CORP.

Inventor： Chih-Kang Yeh

IPC: H03M13/35 ,  G06F11/10 ,  G06F3/06 ,  G11C29/52

CPC classification number: H03M13/353 ,  G06F3/0619 ,  G06F3/064 ,  G06F3/0653 ,  G06F3/0679 ,  G06F11/1068 ,  G11C29/52

Abstract: A decoding method, a memory controlling circuit unit and a memory storage device are provided. The decoding method includes: performing a first type decoding operation for a first frame including a first codeword to obtain a second codeword. The method also includes: recording error estimate information corresponding to the first frame according to an execution result of the first type decoding operation. The method further includes: updating the first codeword in the first frame to the second codeword if the error estimate information matches a first condition; and performing a second type decoding operation for a block code including the first frame.

公开(公告)号：US09690490B2

公开(公告)日：2017-06-27

申请号：US14253886

申请日：2014-04-16

Applicant: PHISON ELECTRONICS CORP.

Inventor： Chih-Kang Yeh ,  Li-Chun Liang

IPC: G06F12/00 ,  G06F3/06 ,  G06F11/00

CPC classification number: G06F3/061 ,  G06F3/0611 ,  G06F3/0619 ,  G06F3/0659 ,  G06F3/0679 ,  G06F11/00 ,  G06F12/00 ,  G06F12/0246 ,  G06F2206/1014

Abstract: A method for writing data, a memory storage device and a memory control circuit unit are provided. The method includes receiving a write command and first data corresponding to the write command, obtaining initial data transmission information of the first data and determining whether the initial data transmission information conforms to a predetermined condition, compressing the first data to second data and writing the second data into a rewritable non-violate memory module if the initial data transmission information conforms to the predetermined condition, and writing the uncompressed first data into the rewritable non-violate memory module if the initial data transmission information does not conform to the predetermined condition.

公开(公告)号：US09652330B2

公开(公告)日：2017-05-16

申请号：US14162784

申请日：2014-01-24

Applicant: PHISON ELECTRONICS CORP.

Inventor： Chih-Kang Yeh

IPC: G06F12/14 ,  G06F11/14

CPC classification number: G06F11/1441

Abstract: A method for data management and a memory storage device and a memory control circuit unit thereof. The method includes: configuring a NVRAM and a VRAM; storing first data which includes writing data from a host system in the NVRAM; storing second data read from a rewritable non-volatile memory module in the VRAM; when the memory storage device is re-powered on after power failure, reading the first data from the NVRAM, so as to write the writing data into the rewritable non-volatile memory module.

公开(公告)号：US09367390B2

公开(公告)日：2016-06-14

申请号：US14161708

申请日：2014-01-23

Applicant: PHISON ELECTRONICS CORP.

Inventor： Chih-Kang Yeh

IPC: G06F11/10 ,  G11C11/56 ,  G06F12/02 ,  G06F3/06

CPC classification number: G06F11/1048 ,  G06F3/061 ,  G06F12/0246 ,  G11C11/5628

Abstract: A memory controlling method, a memory storage device and a memory controlling circuit unit are provided. The method includes: providing a first clock signal to a rewritable non-volatile memory module and reading a first data in the rewritable non-volatile memory module according to the first clock signal; providing a second clock signal to the rewritable non-volatile memory module and writing a second data into the rewritable non-volatile memory module according to the second clock signal. A frequency of the second clock signal is different from a frequency of the first clock signal. Accordingly, an operation speed of the rewritable non-volatile memory module may be increased and probabilities of having errors for some operations are decreased.

Abstract translation: 提供存储器控制方法，存储器存储装置和存储器控制电路单元。 该方法包括：向可重写非易失性存储器模块提供第一时钟信号，并根据第一时钟信号读取可重写非易失性存储器模块中的第一数据; 向所述可重写非易失性存储器模块提供第二时钟信号，并根据所述第二时钟信号将第二数据写入所述可重写非易失性存储器模块。 第二时钟信号的频率与第一时钟信号的频率不同。 因此，可重写易失性存储器模块的操作速度可以增加，并且对于一些操作的错误概率降低。

公开(公告)号：US20160132387A1

公开(公告)日：2016-05-12

申请号：US14572793

申请日：2014-12-17

Applicant: PHISON ELECTRONICS CORP.

Inventor： Chih-Kang Yeh

IPC: G06F11/10 ,  G11C29/52

CPC classification number: G11C29/52 ,  G06F11/1048 ,  G11C29/42 ,  G11C2029/0411

Abstract: A data access method for a rewritable non-volatile memory module is provided. The method includes: filling dummy data to first data in order to generate second data, and writing the second data and an error checking and correcting code (ECC code) corresponding to the second data into a first physical programming unit. The method also includes: reading data stream from the first physical programming unit, wherein the data stream includes third data and the ECC code. The method further includes: adjusting the third data according to a pattern of the dummy data in order to generate fourth data when the third data cannot be corrected by using the ECC code, and using the ECC code to correct the fourth data in order to obtain corrected data, wherein the corrected data is identical to the second data.

Abstract translation: 提供了一种用于可重写非易失性存储器模块的数据访问方法。 该方法包括：将伪数据填充到第一数据以产生第二数据，以及将第二数据和与第二数据相对应的错误校验和纠错码（ECC码）写入第一物理编程单元。 该方法还包括：从第一物理编程单元读取数据流，其中数据流包括第三数据和ECC代码。 该方法还包括：根据伪数据的模式调整第三数据，以便当第三数据不能通过使用ECC码进行校正时生成第四数据，并且使用ECC代码来校正第四数据以获得 校正数据，其中校正数据与第二数据相同。

公开(公告)号：US20160117244A1

公开(公告)日：2016-04-28

申请号：US14557422

申请日：2014-12-01

Applicant: PHISON ELECTRONICS CORP.

Inventor： Chih-Kang Yeh

IPC: G06F12/02 ,  G11C16/28

CPC classification number: G06F12/0246 ,  G06F2212/7205 ,  G11C7/1006 ,  G11C16/10 ,  G11C16/28 ,  G11C16/32 ,  G11C16/3495 ,  G11C2207/102

Abstract: A data writing method for a rewritable non-volatile memory module is provided. The method includes: compressing data to generate first data; determining whether a data length of the first data meets a predetermined condition. The method also includes: if the data length of the first data meets the predetermined condition, writing the first data into a first physical erasing unit among a plurality of physical erasing units; if the data length of the first data does not meet the predetermined condition, generating dummy data according to a predetermined rule, padding the first data with the dummy data to generate second data and writing the second data into the first physical erasing unit. A data length of the second data meets the predetermined condition.

Abstract translation: 提供了一种用于可重写非易失性存储器模块的数据写入方法。 该方法包括：压缩数据以产生第一数据; 确定第一数据的数据长度是否满足预定条件。 该方法还包括：如果第一数据的数据长度满足预定条件，则将第一数据写入多个物理擦除单元中的第一物理擦除单元; 如果第一数据的数据长度不满足预定条件，则根据预定规则产生伪数据，用伪数据填充第一数据以产生第二数据并将第二数据写入第一物理擦除单元。 第二数据的数据长度满足预定条件。

公开(公告)号：US09058256B2

公开(公告)日：2015-06-16

申请号：US13961851

申请日：2013-08-07

Applicant: PHISON ELECTRONICS CORP.

Inventor： Chih-Kang Yeh

IPC: G06F12/10 ,  G06F12/02 ,  G06F3/06 ,  G11C16/10

CPC classification number: G06F12/0246 ,  G06F3/0647 ,  G06F12/0292 ,  G06F2212/7201 ,  G11C16/102

Abstract: A data writing method for a rewritable non-volatile memory module is provided. The method includes selecting at least one physical erasing unit as a global random area and building a global random area searching table for recording update information corresponding to updated logical pages that data stored in the global random area belongs to. The method also includes receiving updated data belonging to a logical page; and determining whether a data dispersedness degree corresponding to the global random area is smaller than a data dispersedness degree threshold. The method further includes, if the data dispersedness degree corresponding to the global random area is smaller than the data dispersedness degree threshold, writing the update data into the global random area and recording update information corresponding to the logical page in the global random area searching table.

Abstract translation: 提供了一种用于可重写非易失性存储器模块的数据写入方法。 所述方法包括：选择至少一个物理擦除单元作为全局随机区域，并构建全局随机区域搜索表，用于记录对应于存储在全球随机区域中的数据所属的更新的逻辑页面的更新信息。 该方法还包括接收属于逻辑页的更新数据; 并且确定与全局随机区域相对应的数据分散度是否小于数据分散度阈值。 该方法还包括：如果与全局随机区域相对应的数据分散度小于数据分散度阈值，则将更新数据写入全局随机区域并将对应于逻辑页面的更新信息记录在全局随机区域搜索表中 。

公开(公告)号：US20140129763A1

公开(公告)日：2014-05-08

申请号：US14151841

申请日：2014-01-10

Applicant: PHISON ELECTRONICS CORP.

Inventor： Chih-Kang Yeh

IPC: G06F12/02

CPC classification number: G06F12/0246 ,  G06F12/04 ,  G06F2212/7209

Abstract: A method for writing updated data into a flash memory module having a plurality of physical pages is provided, wherein each physical page is the smallest writing unit of the flash memory module. The method includes partitioning a physical page into storage segments and configuring a state mark for each storage segment, wherein the state marks indicate the validity of data stored in the storage segments. The method also includes writing the updated data into at least one of the storage segments and changing the state mark corresponding to the storage segment containing the updated data, wherein the state mark corresponding to the storage segment containing the updated data indicates a valid state, and the state marks corresponding to the other storage segments of the physical page not containing the updated data indicate an invalid state. Thereby, the time for writing data into a physical page is effectively shortened.

Abstract translation: 提供了一种用于将更新的数据写入具有多个物理页面的闪存模块的方法，其中每个物理页面是闪存模块的最小写入单元。 该方法包括将物理页面划分为存储段并为每个存储段配置状态标记，其中状态标记指示存储在存储段中的数据的有效性。 该方法还包括将更新后的数据写入至少一个存储段并改变对应于包含更新数据的存储段的状态标记，其中对应于包含更新数据的存储段的状态标记表示有效状态，以及 对应于不包含更新数据的物理页面的其他存储段的状态标记表示无效状态。 从而有效地缩短将数据写入物理页面的时间。

公开(公告)号：US12086419B2

公开(公告)日：2024-09-10

申请号：US17866569

申请日：2022-07-18

Applicant: PHISON ELECTRONICS CORP.

Inventor： Chih-Kang Yeh

IPC: G06F3/06

CPC classification number: G06F3/0616 ,  G06F3/0652 ,  G06F3/0679

Abstract: A partial erasing management method, a memory storage device, and a memory control circuit unit are provided. The method includes: performing a first partial erasing operation on a first physical region among multiple physical regions in a first physical erasing unit to erase first data in the first physical region; after performing the first partial erasing operation on the first physical region, performing a first programming operation on the first physical region to store second data into the first physical region; and in response to at least one of the first partial erasing operation and the first programming operation, updating first status information related to the first physical region.

公开(公告)号：US20230297233A1

公开(公告)日：2023-09-21

申请号：US17721358

申请日：2022-04-15

Applicant: PHISON ELECTRONICS CORP.

Inventor： Chih-Kang Yeh

IPC: G06F3/06

CPC classification number: G06F3/0604 ,  G06F3/0652 ,  G06F3/0679

Abstract: A memory management method configured for a rewritable non-volatile memory module, a memory storage device, and a memory control circuit unit are provided. The rewritable non-volatile memory module includes a plurality of dies, wherein each of the dies includes a plurality of planes, each of the planes includes a plurality of physical erasing units, and a sum of a number of the planes included in the rewritable non-volatile memory module is a first number. The method includes: grouping the plurality of physical erasing units into a plurality of management units. Each of the plurality of physical erasing units included in each of the management units belongs to a different plane, and each of the management units has a second number of the physical erasing units, wherein the second number is less than the first number.