公开(公告)号：US4791075A

公开(公告)日：1988-12-13

申请号：US104478

申请日：1987-10-05

Applicant: Paul T. Lin

Inventor： Paul T. Lin

IPC: H01L23/057 ,  H01L23/498 ,  H01L23/48

CPC classification number: H01L23/057 ,  H01L23/49827 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2224/92247 ,  H01L24/48 ,  H01L2924/00014 ,  H01L2924/01079 ,  H01L2924/0132 ,  H01L2924/01322 ,  H01L2924/01327 ,  H01L2924/14 ,  H01L2924/15173 ,  H01L2924/15312 ,  H01L2924/1532 ,  H01L2924/16152 ,  Y10T29/49139 ,  Y10T29/49146 ,  Y10T29/49153 ,  Y10T29/49162

Abstract: A process for making hermetic, low cost pin grid array (PGA) semiconductor die packages. The process involves die bonding a semiconductor die or integrated circuit chip to a substrate having an interconnect or metallization pattern thereon. The die is electrically connected to the pattern and then the die and the inner bonds are hermetically sealed inside a cap that is smaller than the substrate so that the ends of the metallization pattern are exposed. The leads are then electrically connected, such as by solder or other technique to the exposed ends of the pattern.

Abstract translation: 一种制造密封，低成本针阵列（PGA）半导体管芯封装的工艺。 该方法涉及将半导体管芯或集成电路芯片裸片接合到其上具有互连或金属化图案的衬底。 模具电连接到图案，然后模具和内部结合件密封在小于衬底的帽内，使得金属化图案的端部露出。 然后将引线例如通过焊料或其它技术电连接到图案的暴露端。

公开(公告)号：US4661887A

公开(公告)日：1987-04-28

申请号：US793414

申请日：1985-10-31

Applicant: Paul T. Lin

Inventor： Paul T. Lin

IPC: H01L23/50 ,  H05K1/18 ,  H05K3/34 ,  H05K13/04 ,  H01R9/09

CPC classification number: H05K3/3426 ,  H05K13/0465 ,  H05K2201/10515 ,  H05K2201/10689 ,  H05K2201/10704 ,  H05K2201/1084 ,  H05K2201/10984 ,  Y02P70/613 ,  Y10T29/49144

Abstract: An integrated circuit package having a plurality of leads capable of holding a quantity of solder paste prior to bonding to a printed circuit board or other substrate. The solder paste bearing structure may be straight or spiral grooves, or even a slot or roughened surface, running down at least the lower length of the leads as long as some mechanism is present which will first hold the solder paste or other electrically conductive binder on the lead and then deliver the binder to the end of the lead to produce an electrical and structural bond in a binder flowing operation. Application of the solder paste to the leads is accomplished by simply dipping the package leads into the paste thereby eliminating the need to make a solder mask for the substrate as well as the task of aligning the mask to the substrate.

Abstract translation: 一种集成电路封装，其具有多个引线，其能够在与印刷电路板或其它基板接合之前保持一定量的焊膏。 焊膏支承结构可以是直的或螺旋形的沟槽，或者甚至是槽或粗糙表面，只要存在一些将首先将焊膏或其它导电粘合剂保持在其上的机构，至少沿着引线的较低长度向下延伸 引线，然后将粘合剂输送到引线的末端，以在粘合剂流动操作中产生电和结构粘合。 通过将封装引线简单地浸入糊料中，可以将焊膏施加到引线上，从而不需要为衬底制造焊接掩模以及将掩模对准衬底的任务。

公开(公告)号：US4038488A

公开(公告)日：1977-07-26

申请号：US576298

申请日：1975-05-12

Applicant: Paul T. Lin

Inventor： Paul T. Lin

IPC: H01L23/498 ,  H01L23/538 ,  H01L25/065 ,  H05K5/00

CPC classification number: H01L23/49822 ,  H01L23/5383 ,  H01L25/0655 ,  H01L2924/0002

Abstract: A multilayer ceramic, multi-chip, dual in-line packaging assembly comprises a ceramic substrate with a pair of semiconductor chip receiving cavities therein. A metalization pattern partially embedded within the substrate provides electrical paths for semiconductor chip devices joined thereto to external circuitry. Semiconductor chips are joined to exposed pads within the chip receiving cavities. Metalization spaced from and positioned beneath the semiconductor chip devices completes interconnections between semiconductor chip devices. Exposed finger areas are spaced from one another and about the semiconductor chip receiving cavities. Embedded lines extend from the finger areas to external circuitry and interconnection means extend between finger areas. Finger areas on one side of a chip receiving cavity are offset with respect to the finger areas on the opposite side of the same chip receiving cavity but aligned with the finger areas on an adjacent chip receiving cavity to minimize crossover connections as well as the electrical coupling. An identical bonding design for each cavity also results. A lead frame is brazed to the substrate at its edges. A lid is bonded to the top surface of the substrate to hermetically seal chips within the chip receiving cavities thereby completing assembly of the package.

公开(公告)号：US20120020040A1

公开(公告)日：2012-01-26

申请号：US13136185

申请日：2011-07-26

Applicant: Paul T. Lin ,  Michael B. McShane

Inventor： Paul T. Lin ,  Michael B. McShane

IPC: H05K1/18

CPC classification number: H05K1/144 ,  H01L24/73 ,  H01L25/0652 ,  H01L25/105 ,  H01L25/16 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/48227 ,  H01L2224/4824 ,  H01L2224/48247 ,  H01L2224/4826 ,  H01L2224/73204 ,  H01L2224/73215 ,  H01L2224/73265 ,  H01L2225/1005 ,  H01L2225/1023 ,  H01L2225/1041 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/19105 ,  H01L2924/3511 ,  H05K3/3436 ,  H01L2924/00012 ,  H01L2924/00

Abstract: The present invention discloses the structure and process for fabrication of an electronic package to contain and protect Package-to-Package (P2P) stacked module of integrated circuit (IC) chips. The process includes a step of providing an interposer that includes conductive traces interconnected between pre-designated contact pads disposed on a top and/or bottom surfaces for mounting at least a top or bottom packages of the IC chips with electric terminals contacting the contact pads disposed on the top and/or bottom surface of the interposer. Standoffs and passive components can also be added onto interposer in order to improve solder joints reliability, electrical performance and main board density at the same time. The inclusion of passive components on the interposer could enhance the electrical performance and the testability of the finished package stack.

Abstract translation: 本发明公开了一种用于制造包含并保护集成电路（IC）芯片的封装到封装（P2P）堆叠模块的电子封装的结构和工艺。 该方法包括提供插入件的步骤，该插入件包括在布置在顶部和/或底部表面上的预先指定的接触垫之间互连的导电迹线，用于安装IC芯片的至少顶部或底部封装，其中电气端子与设置的接触焊盘接触 在插入器的顶部和/或底部表面上。 支架和无源元件也可以添加到插入器上，以便同时提高焊点的可靠性，电气性能和主板密度。 将无源部件包含在插入器上可以增强成品封装堆叠的电性能和可测试性。

公开(公告)号：US06784556B2

公开(公告)日：2004-08-31

申请号：US10126328

申请日：2002-04-19

Applicant: Paul T. Lin

Inventor： Paul T. Lin

IPC: H01L2348

CPC classification number: H01L24/05 ,  H01L24/06 ,  H01L24/45 ,  H01L24/48 ,  H01L2224/02166 ,  H01L2224/04042 ,  H01L2224/05553 ,  H01L2224/05554 ,  H01L2224/05624 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/48465 ,  H01L2224/48624 ,  H01L2224/48644 ,  H01L2224/48647 ,  H01L2224/48724 ,  H01L2224/48744 ,  H01L2224/48747 ,  H01L2224/85205 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01029 ,  H01L2924/01074 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/05042 ,  H01L2924/14 ,  H01L2924/19041 ,  H01L2924/19043 ,  H05K1/0268 ,  H05K3/3452 ,  H05K2201/099 ,  H05K2203/049 ,  H01L2924/00014 ,  H01L2924/00

Abstract: The present invention provides a solution to the problem of weakening bond integrity in integrated circuit devices due in part to test probes galling and weakening the interconnect pads during functional and reliability test probing. In doing so, the invention enables a lowering of the chance a bond wire or interconnect pad will be lifted during a wire bonding process or in normal operation of an integrated circuit device.

Abstract translation: 本发明提供了解决集成电路器件中的键合完整性弱的问题，部分原因在于在功能和可靠性测试探测期间测试探针磨损和弱化互连焊盘。 在这样做时，本发明能够降低接合线或互连焊盘在引线接合过程期间或在集成电路器件的正常操作中被提升的机会。

公开(公告)号：US06301121B1

公开(公告)日：2001-10-09

申请号：US09287218

申请日：1999-04-05

Applicant: Paul T. Lin

Inventor： Paul T. Lin

IPC: H05K702

CPC classification number: H01L23/5382 ,  H01L2224/16225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2924/15311 ,  H05K1/0292 ,  H05K1/0298 ,  H05K2201/10545 ,  H05K2201/10674 ,  H05K2201/10734 ,  H01L2924/00014

Abstract: The present invention comprises a single-substrate multiple chip module (MCM) assembly. The MCM assembly includes a repair-package-site ready MCM board having a top surface and a bottom surface, the top surface further includes a plurality of chip connection trace lines include a chip-select line. The MCM assembly further includes a plurality of bare integrated circuit (IC) chips mounted directly on the top surface of the MCM board each chip connected to the plurality of chip connection trace lines on the top surface. The repair-package-site ready MCM board further includes at least a repair-package-site disposed on the bottom surface having a plurality of connection terminals arranged according to a standard repair packaged-chip footprint. Each of the connection terminals is connected to a via connector disposed in the MCM board for electrically connecting to the conductive trace lines on the top surface. The MCM assembly further includes a chip-select jumper means for disconnecting the chip select line for one of the bare IC chips as a disconnected chip and to connect to one of the repair-package-site provided for mounting a repair packaged-chip onto the bottom surface.

Abstract translation: 本发明包括单片多芯片模块（MCM）组件。 MCM组件包括具有顶表面和底表面的修复包装现场准备的MCM板，顶表面还包括多个芯片连接迹线，包括芯片选择线。 MCM组件还包括直接安装在MCM板的顶表面上的多个裸芯片集成电路芯片，每个芯片连接到顶表面上的多个芯片连接迹线。 修理包装现场准备的MCM板还包括至少设置在底表面上的修理包装部位，其具有根据标准修复封装芯片占用面排列的多个连接端子。 每个连接端子连接到设置在MCM板中的通孔连接器，用于电连接到顶表面上的导电迹线。 MCM组件还包括芯片选择跳线装置，用于断开作为断开的芯片的裸IC芯片之一的芯片选择线，并连接到用于将修复封装芯片安装到所述修复包装部位上的一个 底面。

公开(公告)号：US6093969A

公开(公告)日：2000-07-25

申请号：US313562

申请日：1999-05-15

Applicant: Paul T. Lin

Inventor： Paul T. Lin

IPC: H01L23/24 ,  H01L23/495 ,  H01L25/10

CPC classification number: H01L23/24 ,  H01L23/4951 ,  H01L25/105 ,  H01L2224/0401 ,  H01L2224/05599 ,  H01L2224/06136 ,  H01L2224/16 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/4824 ,  H01L2224/48247 ,  H01L2224/48465 ,  H01L2224/73215 ,  H01L2224/854 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L24/48 ,  H01L2924/00014 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/30107 ,  H01L2924/3025

Abstract: The present invention discloses a face-to-face (FTF) stacked integrated circuit (IC) assembly. The FTF stacked IC assembly includes a first and a second substrate-on-bare-chip (SOBC) modules. Each of the first and second SOBC modules includes a printed circuit board (PCB) having a PCB bottom surface overlying an active circuit surface of a bare integrated circuit (IC) chip. The PCB includes a window opened substantially in a central portion of the active circuit surface of the bare IC chip. The bare IC chip includes bare-chip bonding-pads disposed on the active circuit surface in the window and the PCB includes a plurality of PCB bonding pads. Each of the first and second SOBC modules includes a plurality of bonding wires interconnecting the bare-chip bonding pads to the PCB bonding pads. Each of the first and second SOBC modules includes a plurality of solder balls disposed on a PCB top surface of the PCB connected to the PCB bonding pads with a plurality of metal traces disposed on the PCB board. The solder balls of first SOBC module mounted on the solder balls of the second SOBC module constituting a face-to-face (FTF) stacked SOBC assembly.

Abstract translation: 本发明公开了一种面对面（FTF）堆叠集成电路（IC）组件。 FTF堆叠IC组件包括第一和第二裸芯片（SOBC）模块。 第一和第二SOBC模块中的每一个包括印刷电路板（PCB），PCB印刷电路板底表面覆盖裸电路（IC）芯片的有源电路表面。 PCB包括基本上在裸IC芯片的有源电路表面的中心部分开口的窗口。 裸IC芯片包括设置在窗口中的有源电路表面上的裸芯片接合焊盘，并且PCB包括多个PCB焊盘。 第一和第二SOBC模块中的每一个包括将裸芯片接合焊盘互连到PCB焊盘的多个接合线。 第一和第二SOBC模块中的每一个包括多个焊球，其布置在PCB的PCB顶表面上，该PCB顶表面连接到具有设置在PCB板上的多个金属迹线的PCB焊盘。 安装在第二SOBC模块的焊球上的第一SOBC模块的焊球构成面对面（FTF）堆叠的SOBC组件。

公开(公告)号：US5468999A

公开(公告)日：1995-11-21

申请号：US249602

申请日：1994-05-26

Applicant: Paul T. Lin ,  Michael B. McShane

Inventor： Paul T. Lin ,  Michael B. McShane

IPC: H01L23/24 ,  H01L23/31 ,  H01L23/02 ,  H01L23/12 ,  H01L23/48

CPC classification number: H01L24/06 ,  H01L23/24 ,  H01L23/3128 ,  H01L24/49 ,  H01L2224/0401 ,  H01L2224/05554 ,  H01L2224/32225 ,  H01L2224/45015 ,  H01L2224/45144 ,  H01L2224/48011 ,  H01L2224/48095 ,  H01L2224/48227 ,  H01L2224/49109 ,  H01L2224/49174 ,  H01L2224/49175 ,  H01L2224/49431 ,  H01L2224/49433 ,  H01L2224/73265 ,  H01L24/45 ,  H01L24/48 ,  H01L24/73 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01014 ,  H01L2924/01027 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01087 ,  H01L2924/014 ,  H01L2924/10253 ,  H01L2924/12044 ,  H01L2924/15153 ,  H01L2924/1517 ,  H01L2924/15173 ,  H01L2924/15184 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/20751 ,  H01L2924/20752 ,  H01L2924/30107

Abstract: A ball grid array semiconductor device (10) includes a package substrate (14 or 16) having a plurality of conductive traces (18), bond posts (20), and conductive vias (22). A semiconductor die (12) is mounted to the package substrate. Orthogonal wire bonds (28) are used to electrically connect staggered bond pads (26) to corresponding bond posts (20) on the substrate. A liquid encapsulant (40) is used to cover the die, the wire bonds, and portions of the package substrate. In another embodiment, a package substrate (50) includes a lower bonding tier (52) and an upper bonding tier (54). Wire bonds (60) are used to electrically connect an outer row of bond pads (64) to bond posts (20) of lower tier (52), while wire bonds (62) are used to electrically connect an inner row of bond pads (64) to bond posts (20) of an upper tier (54). The loop height of wire bonds (60) is smaller than that of wire bonds (62).

Abstract translation: 球栅阵列半导体器件（10）包括具有多个导电迹线（18），接合柱（20）和导电通孔（22）的封装衬底（14或16）。 半导体管芯（12）安装到封装衬底上。 正交线接合（28）用于将交错的接合焊盘（26）电连接到衬底上的对应的接合柱（20）。 液体密封剂（40）用于覆盖模具，引线键合和封装衬底的部分。 在另一个实施例中，封装衬底（50）包括下结合层（52）和上结合层（54）。 线接合（60）用于将外排的接合焊盘（64）电连接到下层（52）的接合柱（20），而引线接合（62）用于电连接内排接合焊盘 64）到上层（54）的粘合柱（20）。 引线键（60）的环路高度小于引线键合（62）。

公开(公告)号：US5378657A

公开(公告)日：1995-01-03

申请号：US205424

申请日：1994-03-04

Applicant: Paul T. Lin

Inventor： Paul T. Lin

IPC: H01L23/48 ,  H01L21/48 ,  H01L23/10 ,  H01L23/495 ,  H01L23/50 ,  H05K1/02 ,  H05K3/34 ,  H01L21/60

CPC classification number: H05K3/3426 ,  H01L21/4842 ,  H01L23/10 ,  H01L23/49534 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L24/45 ,  H01L24/48 ,  H01L2924/01047 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/15153 ,  H01L2924/1517 ,  H01L2924/16152 ,  H01L2924/30107 ,  H05K1/0271 ,  H05K2201/10689 ,  H05K2201/10909 ,  Y02P70/613 ,  Y10T29/49121

Abstract: A quad leadframe (22') for a CERQUAD is manufactured using conventional cladding and stamping technologies. A first metal layer (12) is provided with multiple cavities (14). A second metal layer (14) is clad to the first metal layer. A leadframe strip (22) can then be stamped from the clad metal. The leadframe has a leads (24) and bonding posts (28). The leads comprise two metal layers, and the bonding posts comprise only the second metal layer. The leadframe can then be used in the assembly of a semiconductor device (32). The portion of the leads external to the package body can be optionally etched to remove the second metal layer.

Abstract translation: 使用传统的包层和冲压技术制造用于CERQUAD的四引线框架（22'）。 第一金属层（12）设置有多个空腔（14）。 第二金属层（14）被包覆到第一金属层。 然后可以从复合金属冲压引线框条（22）。 引线框具有引线（24）和接合柱（28）。 引线包括两个金属层，并且接合柱仅包括第二金属层。 然后可以将引线框架用于半导体器件（32）的组装中。 可以任选地蚀刻包装体外部引线的部分以去除第二金属层。

公开(公告)号：US5329158A

公开(公告)日：1994-07-12

申请号：US964488

申请日：1992-10-21

Applicant: Paul T. Lin

Inventor： Paul T. Lin

IPC: C23C2/08 ,  C23C2/10 ,  C23C2/34 ,  H01L23/495 ,  H01L23/50 ,  H05K1/18 ,  H05K3/34 ,  H01L23/48 ,  H01L29/44 ,  H01L29/52 ,  H01L29/60

CPC classification number: H01L23/49582 ,  H01L23/49579 ,  H05K3/3426 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L24/48 ,  H01L2924/00014 ,  H01L2924/01012 ,  H01L2924/01077 ,  H01L2924/01078 ,  H01L2924/01327 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/181 ,  H05K2201/10689 ,  H05K2201/10909 ,  H05K2201/10984 ,  H05K2201/2081 ,  Y02P70/613

Abstract: An improved semiconductor device is disclosed having a predetermined amount of solder, or other electrically conductive binder adsorbed onto the exterior package leads of the semiconductor device. A de-wettable coating comprising preferably nickel, or alternatively chromium, is plated to a superior portion of the package leads, such that, when the heat is applied to the substrate mounting end of the leads, solder desorbes from the de-wettable layer and flows down the lead to the contact pads on the mounting substrate and forms a solder joint. The amount of solder delivered to the contact pad for joint formation is determined by the thickness of the adsorbed solder layer overlying each package lead. Only enough solder is provided on each lead sufficient to form the joint thus avoiding solder bridging between adjacent contact pads.

Abstract translation: 公开了一种改进的半导体器件，其具有预定量的焊料或吸附到半导体器件的外部封装引线上的其它导电粘合剂。 包含优选镍或可选择的铬的脱湿涂层被电镀到封装引线的上部，使得当将热施加到引线的基板安装端时，来自脱湿层的焊料脱离和 沿着导线流到安装基板上的接触焊盘，并形成焊点。 输送到用于接合形成的接触焊盘的焊料的量由覆盖在每个封装引线上的吸附焊料层的厚度确定。 在每个引线上仅提供足够的焊料以形成接头，从而避免相邻接触焊盘之间的焊料桥接。