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公开(公告)号：US20080216313A1
公开(公告)日：2008-09-11
申请号：US11684583
申请日：2007-03-09
Applicant: Ting-Hao Lin
Inventor： Ting-Hao Lin
IPC: H05K3/10
CPC classification number: H05K1/116 , H05K3/064 , H05K3/427 , H05K2201/09545 , H05K2201/09563 , H05K2201/09736 , Y10T29/41 , Y10T29/49155 , Y10T29/49165
Abstract: A method for fabricating an IC board without a ring structure is provided, in which after the completion of the core board (including the core through hole), the second pattern photoresist layer is used to mask over the first depositing metal layer, and portion of the second depositing metal layer (this portion of the second depositing metal layer is to electrically couple to the conductive circuit of the core through hole). Later, the second depositing metal layer, the first depositing metal layer, the metal layer, and even to the substrate at the innermost layer which are for the portion that are not masked by the second pattern photoresist layer are removed. As a result, the substrate is exposed to form the ringless structure, but which is to couple a conductive line to the core board through hole.
Abstract translation: 提供一种用于制造没有环形结构的IC板的方法，其中在芯板（包括芯通孔）完成之后，使用第二图案光致抗蚀剂层来掩蔽第一沉积金属层，并将部分 第二沉积金属层（第二沉积金属层的该部分电耦合到芯通孔的导电电路）。 之后，去除第二沉积金属层，第一沉积金属层，金属层，甚至去除未被第二图案光刻胶层掩蔽的部分的最内层的基板。 结果，基板被暴露以形成无环结构，但是将导电线耦合到芯板通孔。
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32.发明授权Method for fabricating an interlayer conducting structure of an embedded circuitry 有权一种用于制造嵌入式电路的层间导电结构的方法公开(公告)号：US08161639B2
公开(公告)日：2012-04-24
申请号：US12895824
申请日：2010-09-30
Applicant: Chien-Wei Chang , Ting-Hao Lin , Yu-Te Lu
Inventor： Chien-Wei Chang , Ting-Hao Lin , Yu-Te Lu
IPC: H01K3/10
CPC classification number: H05K3/4679 , H05K1/0269 , H05K3/0035 , H05K3/421 , H05K3/4658 , H05K2201/09918 , Y10T29/49124 , Y10T29/49126 , Y10T29/4913 , Y10T29/49131 , Y10T29/49155 , Y10T29/49165
Abstract: A method for fabricating an interlayer conducting structure of an embedded circuitry is disclosed. In accordance with the method for fabricating an interlayer conducting structure of an embedded circuitry of the present invention, there is no laser conformal mask formed prior to laminating the first and second lamination plates. Instead, after the first and second lamination plates are laminated, a laser boring process is directly conducted to form a via hole. In such a way, even when there is an offset between the first and the second lamination plates in alignment, the risk of short circuit between different layers of lamination plates can be lowered without improving an interlayer offset value.
Abstract translation: 公开了一种用于制造嵌入式电路的层间导电结构的方法。 根据本发明的嵌入式电路的层间导电结构的制造方法，在层叠第一和第二层压板之前不形成激光共形掩模。 相反，在第一和第二层压板层压之后，直接进行激光钻孔工艺以形成通孔。 以这种方式，即使在第一和第二层压板之间存在偏移对准的情况下，也可以在不改善层间偏移值的情况下降低层压板的不同层之间短路的风险。
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公开(公告)号：US08051558B2
公开(公告)日：2011-11-08
申请号：US12329584
申请日：2008-12-06
Applicant: Ting-Hao Lin , Chien-Wei Chang
Inventor： Ting-Hao Lin , Chien-Wei Chang
CPC classification number: H05K1/162 , H05K1/165 , H05K1/167 , H05K3/108 , H05K3/205 , H05K2201/09236 , H05K2201/09881 , Y10T29/49002 , Y10T29/49117 , Y10T29/49124 , Y10T29/49128 , Y10T29/49155
Abstract: A manufacturing method for mainly embedding the passive device structure in the printed circuit board is presented. In this structure, both the source electrode and the ground electrode of the passive device belong to the same level, and includes several source branches and several ground branches that are formed vertically on the inside of the dielectric layer of the circuit board which are connected, respectively, to avoid the conducting between the source electrode and the ground electrode during lamination. When it is in the form of the capacitor structure, through the use of the ultra-fine wiring technique, these source branches and ground branches are separated by a small gap between each other. Therefore, the side face area and quantities of the source branches and ground branches are both increased.
Abstract translation: 提出了一种主要将无源器件结构嵌入印刷电路板的制造方法。 在该结构中，无源器件的源电极和接地电极都属于同一水平，并且包括垂直形成在电路板的电介质层的内部上的数个源极分支和几个接地分支， 以避免在层压期间源电极和接地电极之间的导电。 当它是电容器结构的形式时，通过使用超细布线技术，这些源极分支和接地分支之间彼此间有很小的间隙。 因此，源分支和接地分支的侧面积和数量都增加。
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34.发明申请Method For Fabricating An Interlayer Conducting Structure Of An Embedded Circuitry 有权用于制造嵌入式电路的层间导电结构的方法公开(公告)号：US20110083323A1
公开(公告)日：2011-04-14
申请号：US12895824
申请日：2010-09-30
Applicant: Chien-Wei Chang , Ting-Hao Lin , Yu-Te Lu
Inventor： Chien-Wei Chang , Ting-Hao Lin , Yu-Te Lu
IPC: H05K3/00
CPC classification number: H05K3/4679 , H05K1/0269 , H05K3/0035 , H05K3/421 , H05K3/4658 , H05K2201/09918 , Y10T29/49124 , Y10T29/49126 , Y10T29/4913 , Y10T29/49131 , Y10T29/49155 , Y10T29/49165
Abstract: A method for fabricating an interlayer conducting structure of an embedded circuitry is disclosed. In accordance with the method for fabricating an interlayer conducting structure of an embedded circuitry of the present invention, there is no laser conformal mask formed prior to laminating the first and second lamination plates. Instead, after the first and second lamination plates are laminated, a laser boring process is directly conducted to form a via hole. In such a way, even when there is an offset between the first and the second lamination plates in alignment, the risk of short circuit between different layers of lamination plates can be lowered without improving an interlayer offset value.
Abstract translation: 公开了一种用于制造嵌入式电路的层间导电结构的方法。 根据本发明的嵌入式电路的层间导电结构的制造方法，在层叠第一和第二层压板之前不形成激光共形掩模。 相反，在第一和第二层压板层压之后，直接进行激光钻孔工艺以形成通孔。 以这种方式，即使在第一和第二层压板之间存在偏移对准的情况下，也可以在不改善层间偏移值的情况下降低层压板的不同层之间短路的风险。
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公开(公告)号：US20100309608A1
公开(公告)日：2010-12-09
申请号：US12479810
申请日：2009-06-07
Applicant: Chien-Wei Chang , Ting-Hao Lin , Ya-Hsiang Chen , Yu-Te Lu
Inventor： Chien-Wei Chang , Ting-Hao Lin , Ya-Hsiang Chen , Yu-Te Lu
IPC: H01M6/14
Abstract: A buried capacitor structure including a first conductive metal layer, a first dielectric film, a capacitor, a second dielectric film, and a second conductive metal layer, which are stacked in sequence, wherein the capacitor is buried between the first dielectric film and the second dielectric film, the first conductive metal layer is formed into a first circuit pattern, the second conductive metal layer is formed into a second circuit pattern. The capacitor is a planar comb-shaped capacitor with a positive electrode, a negative electrode, and a capacitor paste filled between the positive electrode and the negative electrode, wherein the positive electrode includes a positive electrode end and a plurality of positive comb branches, the negative electrode includes a negative electrode end and a plurality of negative comb branches, and the positive branches and the negative branches are parallel to and separated from each other.
Abstract translation: 一种埋置电容器结构，其包括依次层叠的第一导电金属层，第一电介质膜，电容器，第二电介质膜和第二导电金属层，其中，所述电容器埋设在所述第一电介质膜和所述第二电介质膜之间 电介质膜，第一导电金属层形成为第一电路图案，第二导电金属层形成第二电路图案。 电容器是具有正极，负极和填充在正极和负极之间的电容器浆料的平面梳状电容器，其中正极包括正极端和多个正梳分支， 负极包括负极端和多个负梳分支，并且正分支和负分支彼此平行并分离。
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Patent Agency Ranking
公开(公告)号：US20100283145A1
公开(公告)日：2010-11-11
申请号：US12435409
申请日：2009-05-05
Applicant: Chien-Wei Chang , Ting-Hao Lin , Yu-Te Lu , Wen-Chun Huang
Inventor： Chien-Wei Chang , Ting-Hao Lin , Yu-Te Lu , Wen-Chun Huang
IPC: H01L23/498
CPC classification number: H01L23/49811 , H01L23/49822 , H01L24/16 , H01L24/81 , H01L2224/0554 , H01L2224/05568 , H01L2224/05573 , H01L2224/13099 , H01L2224/131 , H01L2224/81193 , H01L2224/81801 , H01L2924/00014 , H01L2924/01013 , H01L2924/01029 , H01L2924/01033 , H01L2924/14 , H01L2924/3841 , H01L2924/00 , H01L2224/05599 , H01L2224/0555 , H01L2224/0556
Abstract: A stack structure with copper bumps on an integrated circuit board is disclosed. The stack structure includes a plurality of insulating layers and a plurality of conductive layers which are stacked alternately. The uppermost conductive layer has copper bumps as copper pillar pins for soldering the chip pins of an integrated circuit chip. Because the copper bumps have a certain height, the distance between the copper bumps and the chip pins is shortened, and therefore the solders needed for soldering may be reduced. Also, the shape of the solders is a long strap instead of spheroid due to the cohesion force between the copper bump surfaces and the solders so that the distance between the solders is scaled down and the gaps between the pins are reduced. Thus, the entire size of the integrated circuit board may also be miniatured.
Abstract translation: 公开了一种在集成电路板上具有铜凸块的堆叠结构。 堆叠结构包括交替堆叠的多个绝缘层和多个导电层。 最上层的导电层具有作为用于焊接集成电路芯片的芯片引脚的铜柱引脚的铜凸块。 由于铜凸块具有一定的高度，所以铜凸块和芯片销之间的距离缩短，因此焊接所需的焊料可能会降低。 此外，由于铜凸块表面和焊料之间的内聚力，焊料的形状是长带而不是球体，使得焊料之间的距离被缩小，并且销之间的间隙减小。 因此，集成电路板的整体尺寸也可以是微型的。
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公开(公告)号：US20090294052A1
公开(公告)日：2009-12-03
申请号：US12131932
申请日：2008-06-03
Applicant: Chien-Wei Chang , Ting-Hao Lin , Tu-Te Lu
Inventor： Chien-Wei Chang , Ting-Hao Lin , Tu-Te Lu
IPC: B32B37/00
CPC classification number: B32B37/226 , B32B38/06 , B32B2305/342 , B32B2457/08 , H01L24/24 , H01L24/82 , H01L2224/04105 , H01L2224/32245 , H01L2224/73267 , H01L2224/8203 , H01L2224/83005 , H01L2224/83132 , H05K1/023 , H05K1/185 , H05K1/188 , H05K3/025 , H05K2201/0355 , H05K2201/10636 , H05K2203/063 , Y02P70/611
Abstract: A method for fabricating a component-embedded PCB includes: providing a carrier plate having a plating metal layer plated thereon; disposing an electronic component on the plating metal layer of the carrier plate; laminating a metal layer onto the plating metal layer having the electronic component disposed thereon and the carrier plate by a dielectric film; removing the carrier plate and exposing the plating metal layer; and patterning at least one of the metal layer and the plating metal layer to be a circuit layer.
Abstract translation: 一种用于制造部件嵌入式PCB的方法包括：提供其上镀有电镀金属层的载体板; 将电子部件设置在载体板的电镀金属层上; 通过电介质膜将金属层层叠在其上设置有电子部件的电镀金属层和载体板上; 移除载体板并暴露电镀金属层; 并且将金属层和电镀金属层中的至少一个图案化为电路层。
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公开(公告)号：US07573721B2
公开(公告)日：2009-08-11
申请号：US11749752
申请日：2007-05-17
Applicant: Ting-Hao Lin , Chien-Wei Chang
Inventor： Ting-Hao Lin , Chien-Wei Chang
IPC: H05K1/16
CPC classification number: H05K1/162 , H05K1/165 , H05K1/167 , H05K3/108 , H05K3/205 , H05K2201/09236 , H05K2201/09881 , Y10T29/49002 , Y10T29/49117 , Y10T29/49124 , Y10T29/49128 , Y10T29/49155
Abstract: Embedded passive device structure and its manufacturing method for mainly embedding the passive device structure in the printed circuit board are presented. In this structure, both the source electrode and the ground electrode of the passive device belong to the same level, and includes several source branches and several ground branches that are formed vertically on the inside of the dielectric layer of the circuit board which are connected, respectively, to avoid the conducting between the source electrode and the ground electrode during lamination. When it is in the form of the capacitor structure, through the use of the ultra-fine wiring technique, these source branches and ground branches are separated by a small gap between each other. Therefore, the side face area and quantities of the source branches and ground branches are both increased.
Abstract translation: 介绍了嵌入式无源器件结构及其主要将无源器件结构嵌入印刷电路板的制造方法。 在该结构中，无源器件的源电极和接地电极都属于同一水平，并且包括垂直形成在电路板的电介质层的内部的多个源极分支和几个接地分支， 以避免在层压期间源电极和接地电极之间的导电。 当它是电容器结构的形式时，通过使用超细布线技术，这些源极分支和接地分支之间彼此间有很小的间隙。 因此，源分支和接地分支的侧面积和数量都增加。
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公开(公告)号：US20090154127A1
公开(公告)日：2009-06-18
申请号：US11958384
申请日：2007-12-18
Applicant: Ting-Hao Lin , Chien-Wei Chang
Inventor： Ting-Hao Lin , Chien-Wei Chang
CPC classification number: H05K1/187 , H05K3/205 , H05K2201/10636 , Y02P70/611 , Y10T29/49124
Abstract: Structure of embedded electronic elements in a PCB (printed circuit board) and the method for embedding the structure include assembling the electronic elements (such as a capacitor, a resistor, a diode) on the PCB, and then laminating other circuit layers. A group of electrodes of the electronic elements are aligned to a group of junctions on the PCB, respectively; the electronic elements are assembled on the group of junctions on the PCB; and then a metal layer is laminated on the PCB using gel film (dielectric gel) in which the PCB includes already embedded electronic elements.
Abstract translation: PCB（印刷电路板）中的嵌入式电子元件的结构和嵌入结构的方法包括将电子元件（例如电容器，电阻器，二极管）组装在PCB上，然后层叠其它电路层。 电子元件的一组电极分别对准PCB上的一组接头; 电子元件组装在PCB上的一组接头上; 然后使用其中PCB包括已经嵌入的电子元件的凝胶膜（电介质凝胶）在PCB上层压金属层。
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公开(公告)号：US20090078576A1
公开(公告)日：2009-03-26
申请号：US12329584
申请日：2008-12-06
Applicant: Ting-Hao Lin , Chien-Wei Chang
Inventor： Ting-Hao Lin , Chien-Wei Chang
IPC: C25D5/00
CPC classification number: H05K1/162 , H05K1/165 , H05K1/167 , H05K3/108 , H05K3/205 , H05K2201/09236 , H05K2201/09881 , Y10T29/49002 , Y10T29/49117 , Y10T29/49124 , Y10T29/49128 , Y10T29/49155
Abstract: Embedded passive device structure and its manufacturing method for mainly embedding the passive device structure in the printed circuit board are presented. In this structure, both the source electrode and the ground electrode of the passive device belong to the same level, and includes several source branches and several ground branches that are formed vertically on the inside of the dielectric layer of the circuit board which are connected, respectively, to avoid the conducting between the source electrode and the ground electrode during lamination. When it is in the form of the capacitor structure, through the use of the ultra-fine wiring technique, these source branches and ground branches are separated by a small gap between each other. Therefore, the side face area and quantities of the source branches and ground branches are both increased.
Abstract translation: 介绍了嵌入式无源器件结构及其主要将无源器件结构嵌入印刷电路板的制造方法。 在该结构中，无源器件的源电极和接地电极都属于同一水平，并且包括垂直形成在电路板的电介质层的内部的多个源极分支和几个接地分支， 以避免在层压期间源电极和接地电极之间的导电。 当它是电容器结构的形式时，通过使用超细布线技术，这些源极分支和接地分支之间彼此间有很小的间隙。 因此，源分支和接地分支的侧面积和数量都增加。
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