公开(公告)号：US20190013381A1

公开(公告)日：2019-01-10

申请号：US15656802

申请日：2017-07-21

Applicant: United Microelectronics Corp.

Inventor： En-Chiuan Liou ,  Yu-Cheng Tung ,  Ching-Ling Lin

IPC: H01L29/06 ,  H01L29/78 ,  H01L29/66 ,  H01L21/762

Abstract: A semiconductor structure and a manufacturing method thereof are provided. The semiconductor structure includes a substrate, a first dielectric layer, a first doping layer of a first conductivity type, and a second doping layer of a second conductivity type. The substrate has a fin portion. The first dielectric layer is disposed on the substrate and surrounds the fin portion. The first doping layer of the first conductivity type is disposed on the first dielectric layer and is located on two opposite sidewalls of the fin portion. The second doping layer of the second conductivity type is disposed on the two opposite sidewalls of the fin portion and is located between the fin portion and the first doping layer. The first doping layer covers a sidewall and a bottom surface of the second doping layer.

公开(公告)号：US09984974B1

公开(公告)日：2018-05-29

申请号：US15863986

申请日：2018-01-08

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Ching-Ling Lin ,  Chih-Sen Huang ,  Ching-Wen Hung ,  Jia-Rong Wu ,  Tsung-Hung Chang ,  Yi-Hui Lee ,  Yi-Wei Chen

IPC: H01L21/338 ,  H01L23/528 ,  H01L21/8234 ,  H01L27/06 ,  H01L23/532 ,  H01L21/768

CPC classification number: H01L23/5283 ,  H01L21/76816 ,  H01L21/76829 ,  H01L21/76832 ,  H01L21/76897 ,  H01L21/823475 ,  H01L23/53261 ,  H01L23/53266 ,  H01L27/0629

Abstract: A method for fabricating semiconductor device first includes providing a substrate and a shallow trench isolation (STI) in the substrate, in which the substrate includes a first metal gate and a second metal gate thereon, a first hard mask on the first metal gate and a second hard mask on the second metal gate, and a first interlayer dielectric (ILD) layer around the first metal gate and the second metal gate. Next, the first hard mask and the second hard mask as mask are utilized to remove part of the first ILD layer for forming a recess, and a patterned metal layer is formed in the recess and on the STI.

公开(公告)号：US09899322B2

公开(公告)日：2018-02-20

申请号：US15257921

申请日：2016-09-07

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Ching-Ling Lin ,  Chih-Sen Huang ,  Ching-Wen Hung ,  Jia-Rong Wu ,  Tsung-Hung Chang ,  Yi-Hui Lee ,  Yi-Wei Chen

IPC: H01L21/338 ,  H01L23/528 ,  H01L21/768 ,  H01L27/06 ,  H01L21/8234 ,  H01L23/532

CPC classification number: H01L23/5283 ,  H01L21/76816 ,  H01L21/76829 ,  H01L21/76832 ,  H01L21/76897 ,  H01L21/823475 ,  H01L23/53261 ,  H01L23/53266 ,  H01L27/0629

Abstract: A method for fabricating semiconductor device is disclosed. First, a substrate is provided, in which the substrate includes a first metal gate and a second metal gate thereon, a first hard mask on the first metal gate and a second hard mask on the second metal gate, and a first interlayer dielectric (ILD) layer around the first metal gate and the second metal gate. Next, the first hard mask and the second hard mask are used as mask to remove part of the first ILD layer for forming a recess, and a patterned metal layer is formed in the recess, in which the top surface of the patterned metal layer is lower than the top surfaces of the first hard mask and the second hard mask.

公开(公告)号：US09484263B1

公开(公告)日：2016-11-01

申请号：US14926003

申请日：2015-10-29

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chao-Hung Lin ,  Li-Wei Feng ,  Shih-Hung Tsai ,  Jyh-Shyang Jenq ,  Ching-Ling Lin ,  Yi-Wen Chen ,  Chen-Ming Huang

IPC: H01L21/8234 ,  H01L29/66 ,  H01L21/3105 ,  H01L21/02 ,  H01L21/3213 ,  H01L21/28 ,  H01L29/06 ,  H01L21/311

CPC classification number: H01L21/823437 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/31053 ,  H01L21/31055 ,  H01L21/31144 ,  H01L21/32139 ,  H01L21/823431 ,  H01L21/823456 ,  H01L21/823468 ,  H01L29/6653 ,  H01L29/66545

Abstract: A method of removing a hard mask on a gate includes forming a first gate structure and a second gate structure. The first gate structure includes a first gate, a first hard mask disposed on the first gate and a first spacer surrounding the first gate and the first hard mask, wherein the second gate structure includes a second gate, a second hard mask disposed on the second gate and a second spacer surrounding the second gate and the second hard mask. Later, the first spacer surrounding the first hard mask and the second spacer surrounding the second hard mask are removed. After that, a dielectric layer is formed to cover the first hard mask and the second hard mask. Finally, the second dielectric layer, the first mask layer and the second mask layer are removed.

Abstract translation: 去除栅极上的硬掩模的方法包括形成第一栅极结构和第二栅极结构。 第一栅极结构包括第一栅极，设置在第一栅极上的第一硬掩模和围绕第一栅极和第一硬掩模的第一隔离物，其中第二栅极结构包括第二栅极，设置在第二栅极上的第二硬掩模 栅极和围绕第二栅极和第二硬掩模的第二隔板。 随后，围绕第一硬掩模的第一间隔物和围绕第二硬掩模的第二间隔物被去除。 之后，形成介电层以覆盖第一硬掩模和第二硬掩模。 最后，去除第二电介质层，第一掩模层和第二掩模层。

公开(公告)号：US09324610B2

公开(公告)日：2016-04-26

申请号：US14455939

申请日：2014-08-10

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Ching-Wen Hung ,  Jia-Rong Wu ,  Tsung-Hung Chang ,  Ching-Ling Lin ,  Yi-Hui Lee ,  Chih-Sen Huang ,  Yi-Wei Chen ,  Chun-Hsien Lin

IPC: H01L21/02 ,  H01L21/768 ,  H01L29/78 ,  H01L23/535 ,  H01L29/66 ,  H01L23/485 ,  H01L23/532

CPC classification number: H01L21/76897 ,  H01L21/28518 ,  H01L21/76843 ,  H01L21/76855 ,  H01L23/485 ,  H01L23/53266 ,  H01L23/535 ,  H01L29/665 ,  H01L29/785 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate having at least one metal gate thereon, a source/drain region adjacent to two sides of the at least one metal gate, and an interlayer dielectric (ILD) layer around the at least one metal gate; forming a plurality of contact holes in the ILD layer to expose the source/drain region; forming a first metal layer in the contact holes; performing a first thermal treatment process; and performing a second thermal treatment process.

Abstract translation: 公开了半导体器件的制造方法。 该方法包括以下步骤：提供其上具有至少一个金属栅极的衬底，与所述至少一个金属栅极的两侧相邻的源极/漏极区域以及围绕所述至少一个金属栅极的层间电介质层 ; 在所述ILD层中形成多个接触孔以暴露所述源/漏区; 在所述接触孔中形成第一金属层; 执行第一热处理过程; 并执行第二热处理过程。

公开(公告)号：US20160027892A1

公开(公告)日：2016-01-28

申请号：US14852624

申请日：2015-09-13

Applicant: United Microelectronics Corp.

Inventor： Ching-Ling Lin ,  Chih-Sen Huang ,  Shih-Fang Tzou ,  Chien-Ting Lin ,  Yi-Wei Chen ,  Shi-Xiong Lin ,  Chun-Lung Chen ,  Kun-Yuan Liao ,  Feng-Yi Chang ,  Hsiao-Pang Chou ,  Chia-Lin Lu

IPC: H01L29/49 ,  H01L29/423 ,  H01L27/088

CPC classification number: H01L29/4966 ,  H01L21/28088 ,  H01L21/823456 ,  H01L21/82385 ,  H01L27/088 ,  H01L29/4232 ,  H01L29/517 ,  H01L29/66545

Abstract: The metal gate structure includes at least a substrate, a dielectric layer, first and second trenches, first metal layer and second metal layers, and two cap layers. In particular, the dielectric layer is disposed on the substrate, and the first and second trenches are disposed in the dielectric layer. The width of the first trench is less than the width of the second trench. The first and second metal layers are respectively disposed in the first trench and the second trench, and the height of the first metal layer is less than or equal to the height of the second metal layer. The cap layers are respectively disposed in a top surface of the first metal layer and a top surface of the second metal layer.

Abstract translation: 金属栅极结构至少包括衬底，电介质层，第一和第二沟槽，第一金属层和第二金属层以及两个盖层。 特别地，介电层设置在基板上，并且第一和第二沟槽设置在电介质层中。 第一沟槽的宽度小于第二沟槽的宽度。 第一和第二金属层分别设置在第一沟槽和第二沟槽中，第一金属层的高度小于或等于第二金属层的高度。 盖层分别设置在第一金属层的顶表面和第二金属层的顶表面中。

公开(公告)号：US09209273B1

公开(公告)日：2015-12-08

申请号：US14463677

申请日：2014-08-20

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Ching-Ling Lin ,  Chih-Sen Huang ,  Shih-Fang Tzou ,  Chien-Ting Lin ,  Yi-Wei Chen ,  Shi-Xiong Lin ,  Chun-Lung Chen ,  Kun-Yuan Liao ,  Feng-Yi Chang ,  Hsiao-Pang Chou ,  Chia-Lin Lu

IPC: H01L21/4763 ,  H01L29/66 ,  H01L27/088 ,  H01L29/51 ,  H01L29/49 ,  H01L21/3213 ,  H01L21/8234 ,  H01L21/8238

CPC classification number: H01L29/4966 ,  H01L21/28088 ,  H01L21/823456 ,  H01L21/82385 ,  H01L27/088 ,  H01L29/4232 ,  H01L29/517 ,  H01L29/66545

Abstract: A method for fabricating a metal gate structure includes providing a substrate on which a dielectric layer, a first trench disposed in the dielectric layer, a first metal layer filling up the first trench, a second trench disposed in the dielectric layer, a second metal layer filling up the second trench are disposed, and the width of the first trench is less than the width of the second trench; forming a mask layer to completely cover the second trench; performing a first etching process to remove portions of the first metal layer when the second trench is covered by the mask layer; and performing a second etching process to concurrently remove portions of the first metal layer and portions of the second metal layer after the first etching process.

Abstract translation: 一种用于制造金属栅极结构的方法，包括：提供基板，其上布置介电层，设置在电介质层中的第一沟槽，填充第一沟槽的第一金属层，设置在电介质层中的第二沟槽，第二金属层 设置填充第二沟槽，并且第一沟槽的宽度小于第二沟槽的宽度; 形成掩模层以完全覆盖所述第二沟槽; 当所述第二沟槽被所述掩模层覆盖时，执行第一蚀刻工艺以去除所述第一金属层的部分; 以及执行第二蚀刻工艺，以在第一蚀刻工艺之后同时去除第一金属层的部分和第二金属层的部分。

公开(公告)号：US20150243663A1

公开(公告)日：2015-08-27

申请号：US14187628

申请日：2014-02-24

Applicant: United Microelectronics Corp.

Inventor： Ching-Wen Hung ,  Chih-Sen Huang ,  Jia-Rong Wu ,  Ching-Ling Lin

IPC: H01L27/092 ,  H01L29/417 ,  H01L21/02 ,  H01L29/45 ,  H01L21/8238 ,  H01L21/285

CPC classification number: H01L27/0924 ,  H01L21/28518 ,  H01L21/76843 ,  H01L21/76855 ,  H01L21/76897 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/823828 ,  H01L21/823864 ,  H01L29/41791

Abstract: A method for manufacturing a semiconductor device and a device manufactured using the same are provided. According to a dual silicide approach of the embodiment, a substrate having a first area with plural first metal gates and a second area with plural second metal gates is provided, wherein the adjacent first metal gates and the adjacent second metal gates are separated by an insulation. A dielectric layer is formed on the first and second metal gates and the insulation. The dielectric layer and the insulation at the first area are patterned by a first mask to form a plurality of first openings. Then, a first silicide is formed at the first openings. The dielectric layer and the insulation at the second area are patterned by a second mask to form a plurality of second openings. Then, a second silicide is formed at the second openings.

Abstract translation: 提供一种制造半导体器件的方法和使用其制造的器件。 根据本实施例的双硅化物方法，提供了具有多个第一金属栅极的第一区域和具有多个第二金属栅极的第二区域的基板，其中相邻的第一金属栅极和相邻的第二金属栅极被绝缘体 。 在第一和第二金属栅极和绝缘体上形成电介质层。 介电层和第一区域处的绝缘体通过第一掩模图案化以形成多个第一开口。 然后，在第一开口处形成第一硅化物。 介电层和第二区域处的绝缘体通过第二掩模图案化以形成多个第二开口。 然后，在第二开口处形成第二硅化物。

公开(公告)号：US20240282637A1

公开(公告)日：2024-08-22

申请号：US18613151

申请日：2024-03-22

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Ching-Ling Lin ,  Wen-An Liang ,  Chen-Ming Huang

IPC: H01L21/8234 ,  H01L21/764 ,  H01L27/088 ,  H01L29/06 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L21/823481 ,  H01L21/764 ,  H01L21/823431 ,  H01L27/0886 ,  H01L29/0649 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/785

Abstract: A semiconductor device includes a fin-shaped structure on a substrate, a gate structure on the fin-shaped structure and an interlayer dielectric (ILD) layer around the gate structure, and a single diffusion break (SDB) structure in the ILD layer and the fin-shaped structure. Preferably, the SDB structure includes a bottom portion and a top portion on the bottom portion, in which the top portion and the bottom portion include different widths.

公开(公告)号：US11972984B2

公开(公告)日：2024-04-30

申请号：US18088631

申请日：2022-12-26

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Ching-Ling Lin ,  Wen-An Liang ,  Chen-Ming Huang

IPC: H01L21/8234 ,  H01L21/764 ,  H01L27/088 ,  H01L29/06 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L21/823481 ,  H01L21/764 ,  H01L21/823431 ,  H01L27/0886 ,  H01L29/0649 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/785

Abstract: A semiconductor device includes a fin-shaped structure on a substrate, a gate structure on the fin-shaped structure and an interlayer dielectric (ILD) layer around the gate structure, and a single diffusion break (SDB) structure in the ILD layer and the fin-shaped structure. Preferably, the SDB structure includes a bottom portion and a top portion on the bottom portion, in which the top portion and the bottom portion include different widths.