公开(公告)号：US20190295984A1

公开(公告)日：2019-09-26

申请号：US16283657

申请日：2019-02-22

Applicant: Unimicron Technology Corp.

Inventor： Po-Chen Lin ,  Ra-Min Tain ,  Chun-Hsien Chien ,  Chien-Chou Chen

IPC: H01L23/00 ,  H01L21/56 ,  H01L23/52

Abstract: An embedded chip package includes a circuit board, a chip, a dielectric material layer, and a build-up circuit structure. The circuit board includes a glass substrate and at least one conductive via. The glass substrate has a first surface, a second surface opposite the first surface, and a through-hole penetrating the glass substrate. The conductive via penetrates the glass substrate. The chip is disposed inside the through-hole. The dielectric material layer is filled inside the through-hole and covers the chip. The build-up circuit structure is disposed on the circuit board. The build-up circuit structure is electrically connected to the conductive via. A lower surface of the chip is exposed outside the dielectric material layer.

公开(公告)号：US20250096145A1

公开(公告)日：2025-03-20

申请号：US18964695

申请日：2024-12-02

Applicant: Unimicron Technology Corp.

Inventor： Chin-Sheng Wang ,  Ra-Min Tain ,  Chih-Kai Chan ,  Chun-Hsien Chien

IPC: H01L23/538 ,  H01L23/13 ,  H01L23/373 ,  H01L25/03

Abstract: An electronic packaging structure including a first circuit structure and a second circuit structure is provided. An electronic component is disposed between the first circuit structure and the second circuit structure. At least one of the first circuit structure and the second circuit structure (for example, the second circuit structure) has a cavity. The electronic component is embedded in the cavity, and may be encapsulated between the first circuit structure and the second circuit structure.

公开(公告)号：US12219711B2

公开(公告)日：2025-02-04

申请号：US18155708

申请日：2023-01-17

Applicant: Unimicron Technology Corp.

Inventor： Chun-Hsien Chien ,  Hsin-Hung Lee ,  Hsuan-Yu Lai ,  Yu-Chung Hsieh ,  Hung-Pin Yu

IPC: H01Q1/48 ,  H05K1/11 ,  H05K1/18

Abstract: A bare circuit board is provided, in which the bare circuit board includes a substrate, an antenna, a chip pad, a ground pattern and a trace. The substrate includes a surface. The antenna and the chip pad are formed on the substrate. The ground pattern is formed on the surface. The trace is formed on the surface and isn't connected to the ground pattern. A measuring gap is formed between the trace and an edge of the ground pattern, and the trace includes a first end and a second end. The first end is electrically connected to the chip pad, whereas the second end is electrically connected to the antenna. The bare circuit board is adapted to transmit a signal. The width of the measuring gap is smaller than a quarter of an equivalent wavelength of the signal.

公开(公告)号：US11251350B2

公开(公告)日：2022-02-15

申请号：US16281108

申请日：2019-02-21

Applicant: Unimicron Technology Corp.

Inventor： Yi-Cheng Lin ,  Yu-Hua Chen ,  Chun-Hsien Chien ,  Chien-Chou Chen ,  Cheng-Hui Wu

IPC: H01L33/62 ,  H01L33/52 ,  H01L23/538 ,  H01L23/498 ,  H01L23/31

Abstract: A light-emitting diode package including a carrier structure, a patterned conductive layer, at least one chip, a dielectric layer, at least one first conductive via, a build-up circuit structure, and at least one light-emitting diode is provided. The patterned conductive layer is disposed on the carrier structure. The chip is disposed on the carrier structure. The dielectric layer is disposed on the carrier structure and encapsulates the chip and the patterned conductive layer. The first conductive via penetrates the dielectric layer and is electrically connected to the patterned conductive layer. The build-up circuit structure is disposed on the dielectric layer and electrically connected to the first conductive via. The light-emitting diode is disposed on the build-up circuit structure.

公开(公告)号：US20210398894A1

公开(公告)日：2021-12-23

申请号：US17402635

申请日：2021-08-16

Applicant: Unimicron Technology Corp.

Inventor： Wei-Ti Lin ,  Chun-Hsien Chien ,  Yu-Hua Chen

IPC: H01L23/498 ,  H01L21/48 ,  H05K1/18

Abstract: A package carrier includes a substrate, at least one interposer disposed in at least one opening of the substrate, a conductive structure layer, a first build-up structure, and a second build-up structure. The interposer includes a glass substrate, at least one conductive via, at least one first pad, and at least one second pad. The conductive via passes through the glass substrate, and the first and the second pads are disposed respectively on an upper surface and a lower surface of the glass substrate opposite to each other and are connected to opposite ends of the conductive via. The conductive structure layer is disposed on the substrate and is structurally and electrically connected to the first and the second pads. The first and the second build-up structures are disposed respectively on the first and the second surfaces of the substrate and are electrically connected to the conductive structure layer.

公开(公告)号：US10999939B2

公开(公告)日：2021-05-04

申请号：US16535102

申请日：2019-08-08

Applicant: Unimicron Technology Corp.

Inventor： Chun-Hsien Chien ,  Wen-Liang Yeh ,  Wei-Ti Lin

IPC: H05K7/10 ,  H05K7/12 ,  H05K3/46 ,  H05K1/11 ,  H05K3/40 ,  H05K3/00

Abstract: A circuit carrier board includes a first build-up layer structure, a substrate, an adhesive layer, and a conductive structure. The first build-up layer includes a plurality of first dielectric layers and a plurality of first circuit layers original stacked. The substrate includes a base and a second build-up layer structure disposed on the base. The second build-up layer structure includes a plurality of second dielectric layers and a plurality of second circuit layer original stacked. A top most layer of the second circuit layers is exposed outside of the second dielectric layers. The conductive structure penetrates through the first dielectric layers, the first circuit layers and the adhesive layer, and contacts with the top most layer of the second circuit layers. The conductive structure electrical connects the first circuit layers to the second circuit layers. A manufacturing method of the circuit carrier board is also provided.

公开(公告)号：US10950687B2

公开(公告)日：2021-03-16

申请号：US16874691

申请日：2020-05-15

Applicant: Unimicron Technology Corp.

Inventor： Yu-Hua Chen ,  Fu-Yang Chen ,  Chun-Hsien Chien ,  Chien-Chou Chen ,  Wei-Ti Lin

IPC: H01L23/522 ,  H01L23/532 ,  H01L23/15 ,  H01L49/02 ,  H01L23/498

Abstract: A manufacturing method of a substrate structure includes the following steps. A first build-up circuit structure is formed. At least one copper pillar is formed on the first build-up circuit structure. A dielectric layer is formed on the first build-up circuit structure, and the dielectric layer wraps the copper pillar. A second build-up circuit structure and a capacitive element are formed on the dielectric layer. In particular, the second build-up circuit structure and the first build-up circuit structure are respectively located at two opposite sides of the dielectric layer. The capacitive element is disposed in a capacitive element setting region within the second build-up circuit structure. The copper pillar penetrates the dielectric layer and is electrically connected to the second build-up circuit structure and the first build-up circuit structure.

公开(公告)号：US20210076508A1

公开(公告)日：2021-03-11

申请号：US16950910

申请日：2020-11-18

Applicant: Unimicron Technology Corp.

Inventor： Wei-Ti Lin ,  Chun-Hsien Chien ,  Chien-Chou Chen ,  Fu-Yang Chen ,  Ra-Min Tain

IPC: H05K3/46 ,  H05K3/40 ,  H05K3/42 ,  H05K3/28 ,  H05K3/30 ,  H05K1/11 ,  H05K1/18 ,  H05K3/00

Abstract: A circuit carrier board structure includes a first substrate, a second substrate, an adhesive layer, and a plurality of contact pads. The first substrate includes a first surface and a second surface, and also includes a plurality of first build-up layers sequentially stacked. The first build-up layers include a first dielectric layer and a first circuit layer. The second substrate includes a third surface and a fourth surface, and also includes a plurality of second build-up layers sequentially stacked. The second build-up layers include a second dielectric layer and a second circuit layer. The second surface is combined to the third surface. The connection pads are on the first surface and electrically connected to the first circuit layer. The first substrate is electrically connected to the second substrate. A manufacturing method of the circuit carrier board structure is also provided.

公开(公告)号：US10888001B2

公开(公告)日：2021-01-05

申请号：US16244113

申请日：2019-01-10

Applicant: Unimicron Technology Corp.

Inventor： Wei-Ti Lin ,  Chun-Hsien Chien ,  Chien-Chou Chen ,  Fu-Yang Chen ,  Ra-Min Tain

IPC: H05K7/10 ,  H05K3/46 ,  H05K3/40 ,  H05K3/42 ,  H05K3/28 ,  H05K3/30 ,  H05K1/11 ,  H05K1/18 ,  H05K3/00

Abstract: A circuit carrier board structure includes a first substrate, a second substrate, an adhesive layer, and a plurality of contact pads. The first substrate includes a first surface and a second surface, and also includes a plurality of first build-up layers sequentially stacked. The first build-up layers include a first dielectric layer and a first circuit layer. The second substrate includes a third surface and a fourth surface, and also includes a plurality of second build-up layers sequentially stacked. The second build-up layers include a second dielectric layer and a second circuit layer. The second surface is combined to the third surface. The connection pads are on the first surface and electrically connected to the first circuit layer. The first substrate is electrically connected to the second substrate. A manufacturing method of the circuit carrier board structure is also provided.

公开(公告)号：US20200273948A1

公开(公告)日：2020-08-27

申请号：US16874691

申请日：2020-05-15

Applicant: Unimicron Technology Corp.

Inventor： Yu-Hua Chen ,  Fu-Yang Chen ,  Chun-Hsien Chien ,  Chien-Chou Chen ,  Wei-Ti Lin

IPC: H01L49/02 ,  H01L23/522 ,  H01L23/498 ,  H01L23/532 ,  H01L23/15

Abstract: A manufacturing method of a substrate structure includes the following steps. A first build-up circuit structure is formed. At least one copper pillar is formed on the first build-up circuit structure. A dielectric layer is formed on the first build-up circuit structure, and the dielectric layer wraps the copper pillar. A second build-up circuit structure and a capacitive element are formed on the dielectric layer. In particular, the second build-up circuit structure and the first build-up circuit structure are respectively located at two opposite sides of the dielectric layer. The capacitive element is disposed in a capacitive element setting region within the second build-up circuit structure. The copper pillar penetrates the dielectric layer and is electrically connected to the second build-up circuit structure and the first build-up circuit structure.