公开(公告)号：US20230005863A1

公开(公告)日：2023-01-05

申请号：US17481943

申请日：2021-09-22

Applicant: YANGTZE MEMORY TECHNOLOGIES CO., LTD.

Inventor： Yuancheng Yang ,  Kun Zhang ,  Wenxi Zhou ,  Zhiliang Xia ,  Liang Chen ,  Yanhong Wang ,  Wei Liu

IPC: H01L23/00 ,  H01L25/065 ,  H01L25/18 ,  H01L25/00

Abstract: In certain aspects, a three-dimensional (3D) memory device includes a first semiconductor structure, a second semiconductor structure, and a bonding interface between the first and the second semiconductor structures. The first semiconductor structure includes an array of NAND memory strings, a first peripheral circuit of the array of NAND memory strings including a first transistor, a polysilicon layer between the array of NAND memory strings and the first peripheral circuit, and a first semiconductor layer in contact with the first transistor. The polysilicon layer is in contact with sources of the array of NAND memory strings. The second semiconductor structure includes a second peripheral circuit of the array of NAND memory strings including a second transistor, and a second semiconductor layer in contact with the second transistor. The second semiconductor layer is between the bonding interface and the second peripheral circuit. The first semiconductor layer is between the polysilicon layer and the second semiconductor layer.

公开(公告)号：US20230005859A1

公开(公告)日：2023-01-05

申请号：US17480949

申请日：2021-09-21

Applicant: YANGTZE MEMORY TECHNOLOGIES CO., LTD.

Inventor： Liang Chen ,  Wei Liu ,  Yanhong Wang ,  Zhiliang Xia ,  Wenxi Zhou ,  Kun Zhang ,  Yuancheng Yang

IPC: H01L23/00 ,  H01L25/065 ,  H01L25/18 ,  H01L25/00

Abstract: In certain aspects, a three-dimensional (3D) memory device includes a first semiconductor structure, a second semiconductor structure, a third semiconductor structure, a first bonding interface between the first semiconductor structure and the second semiconductor structure, and a second bonding interface between the second semiconductor structure and the third semiconductor structure. The first semiconductor structure includes an array of NAND memory strings and a first semiconductor layer in contact with sources of the array of NAND memory strings. The second semiconductor structure includes a first peripheral circuit of the array of NAND memory strings including a first transistor, and a second semiconductor layer in contact with the first transistor. A third semiconductor structure includes a second peripheral circuit of the array of NAND memory strings including a second transistor, and a third semiconductor layer in contact with the second transistor. The second semiconductor layer is between the first bonding interface and the first peripheral circuit. The second peripheral circuit is between the second bonding interface and the third semiconductor layer.

公开(公告)号：US20220336436A1

公开(公告)日：2022-10-20

申请号：US17858695

申请日：2022-07-06

Applicant: YANGTZE MEMORY TECHNOLOGIES CO., LTD.

Inventor： Kun Zhang ,  Linchun Wu ,  Wenxi Zhou ,  Zhiliang Xia ,  Zongliang Huo

IPC: H01L25/18 ,  H01L23/00 ,  H01L25/065 ,  H01L25/00

Abstract: Embodiments of 3D memory devices and methods for forming the same are disclosed. In an example, a 3D memory device includes a memory stack comprising interleaved conductive layers and dielectric layers, a plurality of semiconductor layers contacted with each other and located adjacent to the memory stack, a plurality of channel structures each extending vertically through the memory stack and at least one of the semiconductor layers, a source contact in contact with at least one of the semiconductor layers, and a contact pad located on one side of the semiconductor layers that are away from the memory stack.

公开(公告)号：US20220310648A1

公开(公告)日：2022-09-29

申请号：US17655025

申请日：2022-03-16

Applicant: Yangtze Memory Technologies Co., Ltd.

Inventor： Xiaolong Du ,  Wanbo Geng ,  Zhiliang Xia ,  Xiaoxin Liu ,  Tingting Gao ,  Changzhi Sun

IPC: H01L27/11582 ,  H01L27/11556 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/11565 ,  H01L27/1157

Abstract: A method for forming a three-dimensional memory device includes forming an alternating dielectric stack on a substrate and forming an opening extending partially through the alternating dielectric stack. The opening exposes sidewalls of the alternating dielectric stack. The method also includes disposing a protection layer in the opening and on the exposed sidewalls of the alternating dielectric stack. The method further includes extending the opening through the alternating dielectric stack and forming channel layers in the extended opening.

公开(公告)号：US20220157847A1

公开(公告)日：2022-05-19

申请号：US17117690

申请日：2020-12-10

Applicant: YANGTZE MEMORY TECHNOLOGIES CO., LTD.

Inventor： Kun Zhang ,  Linchun Wu ,  Wenxi Zhou ,  Zhiliang Xia ,  Zongliang Huo

IPC: H01L27/11582 ,  H01L25/065 ,  H01L25/18 ,  H01L23/00 ,  H01L27/11556 ,  H01L29/04 ,  H01L29/16 ,  H01L29/10 ,  H01L21/225 ,  H01L21/02 ,  H01L21/3205 ,  H01L21/3115 ,  H01L21/3215 ,  H01L21/311 ,  H01L21/3213

Abstract: A 3D memory device includes a memory stack including interleaved stack conductive layers and stack dielectric layers, a semiconductor layer, and a channel structure extending vertically through the memory stack into the semiconductor layer. A first lateral dimension of a first portion of the channel structure facing the semiconductor layer is greater than a second lateral dimension of a second portion of the channel structure facing the memory stack. The channel structure includes a memory film and a semiconductor channel A first doping concentration of part of the semiconductor channel in the first portion of the channel structure is greater than a second doping concentration of part of the semiconductor channel in the second portion of the channel structure.

公开(公告)号：US20220093645A1

公开(公告)日：2022-03-24

申请号：US17544814

申请日：2021-12-07

Applicant: YANGTZE MEMORY TECHNOLOGIES CO., LTD.

Inventor： Linchun Wu ,  Shan Li ,  Zhiliang Xia ,  Kun Zhang ,  Wenxi Zhou ,  Zongliang Huo

IPC: H01L27/11582 ,  H01L21/8234 ,  H01L29/417

Abstract: Embodiments of 3D memory devices and methods for forming the same are disclosed. In an example, a 3D memory device includes a doped region of a substrate. The doped region includes dopants of a first type. The 3D memory device also includes a semiconductor layer on the doped region. The semiconductor layer includes dopants of a second type. The first type and the second type are different from each other. The 3D memory device also includes a memory stack having interleaved conductive layers and dielectric layers on the semiconductor layer. The 3D memory device further includes a channel structure extending vertically through the memory stack and the semiconductor layer into the doped region, a semiconductor plug extending vertically into the doped region, the semiconductor plug comprising dopants of the second type, and a source contact structure extending vertically through the memory stack to be in contact with the semiconductor plug.

公开(公告)号：US20220084944A1

公开(公告)日：2022-03-17

申请号：US17534312

申请日：2021-11-23

Applicant: YANGTZE MEMORY TECHNOLOGIES CO., LTD.

Inventor： Di Wang ,  Wenxi Zhou ,  Zhiliang Xia ,  Zhong Zhang

IPC: H01L23/528 ,  H01L21/768 ,  H01L27/11524 ,  H01L27/11565 ,  H01L23/522 ,  H01L27/11556 ,  H01L27/11582 ,  H01L27/1157 ,  H01L27/11519

Abstract: In an example of the present disclosure, 3D memory device includes a memory array structure and a staircase structure dividing the memory array structure into a first memory array structure and a second memory array structure along a lateral direction. The staircase structure includes a plurality of stairs, and a bridge structure in contact with the first memory array structure and the second memory array structure. A stair of the plurality of stairs includes a conductor portion on a top surface of the stair and electrically connected to the bridge structure, and a dielectric portion at a same level and in contact with the conductor portion. The stair is electrically connected to at least one of the first memory array structure and the second memory array structure. The conductor portion includes a portion overlapping with an immediately-upper stair and in contact with the dielectric portion and the bridge structure.

公开(公告)号：US20220037234A1

公开(公告)日：2022-02-03

申请号：US17020473

申请日：2020-09-14

Applicant: YANGTZE MEMORY TECHNOLOGIES CO., LTD.

Inventor： Linchun Wu ,  Kun Zhang ,  Zhong Zhang ,  Wenxi Zhou ,  Zhiliang Xia

IPC: H01L23/48 ,  H01L21/48 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11573 ,  H01L27/11582

Abstract: Embodiments of methods for forming contact structures and semiconductor devices thereof are disclosed. In an example, a semiconductor device includes an insulating layer, a conductive layer over the insulating layer, and a spacer structure in the conductive layer and in contact with the insulating layer. The semiconductor device also includes a first contact structure in the spacer structure and extending vertically through the insulating layer. The first contact structure includes a first contact portion and a second contact portion in contact with each other. An upper surface of the second contact portion is coplanar with an upper surface of the conductive layer.

公开(公告)号：US11177270B2

公开(公告)日：2021-11-16

申请号：US17080697

申请日：2020-10-26

Applicant: YANGTZE MEMORY TECHNOLOGIES CO., LTD.

Inventor： Wenyu Hua ,  Fandong Liu ,  Zhiliang Xia

IPC: H01L27/11565 ,  H01L27/11582

Abstract: Embodiments of a three-dimensional (3D) memory device are provided. A method for forming a 3D memory device is disclosed. A dielectric stack including interleaved sacrificial layers and dielectric layers is formed over a substrate. Channel holes and contact holes are formed through the dielectric stack. The contact holes extend vertically into the substrate and are each surrounded by channel holes of nominally equal lateral distances to the respective contact hole in a plan view. A channel structure is formed in each of the channel holes. A memory stack having interleaved conductive layers and dielectric layers is formed by replacing, through the contact holes, the sacrificial layers in the dielectric stack with the conductive layers. A spacer is formed along a sidewall of each of the contact holes to cover the conductive layers of the memory stack. A contact is formed over the spacer in each of the contact holes. The contact is electrically connected to a common source of the channel structures.

公开(公告)号：US11164633B2

公开(公告)日：2021-11-02

申请号：US17112403

申请日：2020-12-04

Applicant: Yangtze Memory Technologies Co., Ltd.

Inventor： Zongliang Huo ,  Jun Liu ,  Zhiliang Xia ,  Li Hong Xiao

IPC: G11C16/08 ,  G11C16/04 ,  H01L27/11556 ,  H01L27/11573 ,  H01L27/11582 ,  H01L29/792 ,  H01L29/423 ,  H01L29/66 ,  H01L29/786

Abstract: A memory device includes a first semiconductor structure and a second semiconductor structure. The first semiconductor structure includes a first substrate and one or more peripheral devices on the first substrate. The second semiconductor structure includes a first set of conductive lines electrically coupled with a first set of a plurality of vertical structures and a second set of conductive lines electrically coupled with a second set of the plurality of vertical structures different from the first set of the plurality of vertical structures. The first set of conductive lines are vertically distanced from one end of the plurality of vertical structures and the second set of conductive lines are vertically distanced from an opposite end of the plurality of vertical structures.