公开(公告)号：US20130241595A1

公开(公告)日：2013-09-19

申请号：US13887675

申请日：2013-05-06

Applicant: ELEMENT CXI, LLC

Inventor： Steven Hennick Kelem ,  John M. Rudosky ,  Brian A. Box ,  Stephen L. Wasson

IPC: H03K19/173

CPC classification number: H03K19/173 ,  G06F9/3897 ,  G06F11/1423 ,  G06F11/1428 ,  G06F15/7867 ,  H03K19/007 ,  H03K19/17756

Abstract: The exemplary embodiments provide a reconfigurable integrated circuit architecture comprising: a configurable circuit element configurable for a plurality of data operations, each data operation corresponding to a context of a plurality of contexts; a plurality of input queues; a plurality of output queues; one or more configuration and control registers to store, for each context of the plurality of contexts, a plurality of configuration bits, a run status bit, and a plurality of bits designating at least one data input queue and at least one data output queue; and an element controller coupled to the configurable circuit element and to the one or more configuration and control registers, the element controller to allow loading of a context configuration and execution of a data operation upon the arrival of input data in the context-designated data input queue when the context run status is enabled and the context-designated data output queue has a status to accept output data.

Abstract translation: 示例性实施例提供可重构集成电路架构，其包括：可配置用于多个数据操作的可配置电路元件，每个数据操作对应于多个上下文的上下文; 多个输入队列; 多个输出队列; 一个或多个配置和控制寄存器，用于为多个上下文的每个上下文存储指定至少一个数据输入队列和至少一个数据输出队列的多个配置位，运行状态位和多个位; 以及耦合到所述可配置电路元件和所述一个或多个配置和控制寄存器的元件控制器，所述元件控制器允许在上下文指定的数据输入中输入数据到达时加载上下文配置和执行数据操作 上下文运行状态被启用并且上下文指定的数据输出队列具有接受输出数据的状态时的队列。

公开(公告)号：US20130138913A1

公开(公告)日：2013-05-30

申请号：US13748186

申请日：2013-01-23

Applicant: Element CXI, LLC

Inventor： Brian A. Box ,  John M. Rudosky ,  Steven Hennick Kelem ,  Stephen L. Wasson

IPC: G06F12/06

CPC classification number: G06F12/0646 ,  G06F9/3897 ,  G06F11/1423 ,  G06F11/1428 ,  G06F15/7867 ,  H03K19/007 ,  H03K19/17752 ,  H03K19/17756

Abstract: The exemplary embodiments provide a reconfigurable integrated circuit capable of on-chip configuration and reconfiguration, comprising: a plurality of configurable composite circuit elements; a configuration and control bus; a memory; and a sequential processor. Each composite circuit element comprises: a configurable circuit; and an element interface and control circuit, the element interface and control circuit comprising an element controller and at least one configuration and control register to store one or more configuration and control words. The configuration and control bus is coupled to the plurality of configurable composite circuit elements, and comprises a plurality of address and control lines and a plurality of data lines. The sequential processor can write configurations to the configuration and control registers of an addressed configurable composite circuit element to configure or reconfigure the configurable circuit.

Abstract translation: 示例性实施例提供能够进行片上配置和重新配置的可重构集成电路，包括：多个可配置复合电路元件; 配置和控制总线; 记忆 和顺序处理器。 每个复合电路元件包括：可配置电路; 元件接口和控制电路，所述元件接口和控制电路包括元件控制器和至少一个配置和控制寄存器，用于存储一个或多个配置和控制字。 配置和控制总线耦合到多个可配置复合电路元件，并且包括多个地址和控制线以及多条数据线。 顺序处理器可以将配置写入寻址的可配置复合电路元件的配置和控制寄存器，以配置或重新配置可配置电路。

公开(公告)号：US20110055834A1

公开(公告)日：2011-03-03

申请号：US12550813

申请日：2009-08-31

Applicant: Sushil R. Meda ,  Ginger Dusek ,  Nathaniel M. Holobinko ,  Rishi Tank ,  Rahul Solan ,  Keith Wright

Inventor： Sushil R. Meda ,  Ginger Dusek ,  Nathaniel M. Holobinko ,  Rishi Tank ,  Rahul Solan ,  Keith Wright

IPC: G06F9/46

CPC classification number: G06F11/1428 ,  G06F11/1402 ,  G06F11/3466 ,  G06F2201/81 ,  G06F2201/87 ,  G06Q10/10

Abstract: A system for enrollment processing optimization for controlling batch job processing traffic transmitted to a mainframe computer includes an enrollment data input operations system operatively coupled to the mainframe computer and configured to provide a universal front end for data entry of enrollment information. Enrollment records based on the enrollment information is then created. A database system stores the enrollment records, and a workflow application module operatively coupled to the database system is configured to manage processing of the enrollment records and manage transmission of the enrollment records to the mainframe computer for batch processing. A batch throttling control module operatively coupled to the workflow application module and to the mainframe computer controls the rate and the number of enrollment records transmitted by the workflow application module to the mainframe computer for batch processing.

Abstract translation: 用于控制传输到大型计算机的批量作业处理流量的用于注册处理优化的系统包括可操作地耦合到大型计算机并被配置为提供用于登记信息的数据输入的通用前端的注册数据输入操作系统。 然后创建基于注册信息的注册记录。 数据库系统存储注册记录，并且可操作地耦合到数据库系统的工作流应用模块被配置为管理注册记录的处理并且管理注册记录的传送到主机计算机以进行批处理。 可操作地耦合到工作流程应用程序模块和主机计算机的批量调节控制模块控制由工作流应用程序模块发送到大型计算机以进行批处理的登记记录的速率和数量。

公开(公告)号：US06574744B1

公开(公告)日：2003-06-03

申请号：US09356520

申请日：1999-07-19

Applicant: Heinz Kantz ,  Oliver Scheck ,  Peter Metzner

Inventor： Heinz Kantz ,  Oliver Scheck ,  Peter Metzner

IPC: H04L122

CPC classification number: G06F11/3055 ,  G06F11/1425 ,  G06F11/1428 ,  G06F11/3006 ,  G06F2213/0038 ,  H04L41/12 ,  H04L41/14

Abstract: A method of determining a uniform global view (GS) of the system status of a distributed computer network (VRNW) comprising at least three computers (R1, R2, R3) is provided in that the computers exchange messages over communication links (KV12, KV13, KV32) in successive transmission rounds, with each of the computers receiving a message from each of the other computers in each transmission round in the absence of an error. In each transmission round, each of the computers evaluates messages received from the other computers and, based on the result of the evaluation, assigns one of at least three differently defined computer states to each of the other computers and determines a local view (LS) of the system status therefrom. The computers exchange the local views of the system status determined by them, and each of the computers determines a uniform global view (GS) of the system status from the local views exchanged.

Abstract translation: 提供了一种确定包括至少三台计算机（R1，R2，R3）的分布式计算机网络（VRNW）的系统状态的统一全局视图（GS）的方法，其中计算机通过通信链路（KV12，KV13 ，KV32），其中每个计算机在每个传输轮中从每个传输轮中接收来自每个其他计算机的消息，在没有错误的情况下。 在每个传输轮中，每个计算机评估从其他计算机接收的消息，并且基于评估结果，将至少三个不同定义的计算机状态中的一个分配给每个其他计算机，并确定本地视图（LS） 的系统状态。 计算机交换由它们确定的系统状态的本地视图，并且每个计算机从交换的本地视图确定系统状态的统一全局视图（GS）。

公开(公告)号：US12026055B2

公开(公告)日：2024-07-02

申请号：US17109041

申请日：2020-12-01

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Yang Seok Ki ,  Dong Gi Daniel Lee ,  Sung Wook Ryu ,  Ehsan Najafabadi

IPC: G06F11/14 ,  G06F3/06 ,  G06F11/07 ,  G06F11/10 ,  G06F11/20 ,  G06F11/30 ,  G06F11/32 ,  G06F11/34 ,  G06F12/0882 ,  G06F12/1009

CPC classification number: G06F11/1428 ,  G06F3/0619 ,  G06F3/0634 ,  G06F3/0644 ,  G06F3/0649 ,  G06F3/065 ,  G06F3/0673 ,  G06F3/0679 ,  G06F11/0772 ,  G06F11/1068 ,  G06F11/1076 ,  G06F11/1484 ,  G06F11/203 ,  G06F11/2089 ,  G06F11/2094 ,  G06F11/3034 ,  G06F11/3037 ,  G06F11/3072 ,  G06F11/327 ,  G06F11/3409 ,  G06F12/0882 ,  G06F12/1009 ,  G06F2201/85 ,  G06F2212/262

Abstract: A storage device, and a method for operating a storage device. In some embodiments, the storage device includes storage media, and the method includes: determining, by the storage device, that the storage device is in a fault state from which partial recovery is possible by operating the storage device in a first read-only mode; and operating the storage device in the first read-only mode, the operating in the first read-only mode including: determining that the age of a first data item stored in a page of the storage device has exceeded a threshold age, and copying the first data item into a rescue space in the storage device.

公开(公告)号：US11645155B2

公开(公告)日：2023-05-09

申请号：US17249155

申请日：2021-02-22

Applicant: NXP B.V.

Inventor： Arjun Pal Chowdhury ,  Nancy Hing-Che Amedeo ,  Jehoda Refaeli

IPC: G06F11/00 ,  G06F11/14 ,  G06F11/07 ,  G06F13/40

CPC classification number: G06F11/141 ,  G06F11/0772 ,  G06F11/1428 ,  G06F11/1441 ,  G06F13/4027 ,  G06F13/4068

Abstract: A data processing system includes a system interconnect, a first master, and a bridge circuit. The bridge circuit is coupled between the first master and the system interconnect. The bridge circuit is configured to, in response to occurrence of an error in the first master, isolate the first master from the system interconnect, wherein the isolating by the bridge circuit is performed while the first master has one or more outstanding issued write commands to the system interconnect which have not been completed. The bridge circuit is further configured to, after isolating the first master from the system interconnect, complete the one or more outstanding issued write commands while the first master remains isolated from the system interconnect.

公开(公告)号：US10055380B2

公开(公告)日：2018-08-21

申请号：US15862801

申请日：2018-01-05

Applicant: International Business Machines Corporation

Inventor： Gerald K. Bartley ,  Darryl J. Becker ,  Matthew S. Doyle ,  Mark J. Jeanson ,  Mark O. Maxson

IPC: G06F13/00 ,  G06F13/42 ,  G06F13/40 ,  G06F11/14

CPC classification number: G06F13/4291 ,  G06F11/1428 ,  G06F13/4018 ,  G06F13/4068 ,  G06F13/4282

Abstract: A lane within a processor bus that communicatively connects a transmitter and a receiver is dynamically assigned as a clock lane. The clock lane subsequently transmits a reference clock signal to coordinate data communications from the transmitter to the receiver. The clock lane may be assigned by determining signal margins of various lanes of the processor bus. The signal margins are determined by the transmitter sending a test pattern upon the various lanes and analyzing the received test pattern at the receiver. A dynamically assigned clock lane results increased overall signal integrity of communications between the transmitter and receiver. Further, a dynamically assigned clock lane may result in different lanes being assigned as the clock lane at distinct boot up instances, adding to the complexity of the unauthorized user determining the operational logic of the transmitter.

公开(公告)号：US09971463B2

公开(公告)日：2018-05-15

申请号：US14868804

申请日：2015-09-29

Applicant: SYNAPTICS INCORPORATED

Inventor： Petr Shepelev ,  Eric Scott Bohannon ,  Kasra Khazeni

IPC: G06F3/044 ,  G06F3/041 ,  G06F3/0354 ,  G06F11/14 ,  G06F11/00

CPC classification number: G06F3/044 ,  G06F3/03547 ,  G06F3/0416 ,  G06F3/0418 ,  G06F11/00 ,  G06F11/002 ,  G06F11/004 ,  G06F11/006 ,  G06F11/008 ,  G06F11/142 ,  G06F11/1423 ,  G06F11/1428 ,  G06F2201/81 ,  G06F2203/04101

Abstract: This disclosure generally provides an input device that includes a matrix sensor that includes a plurality of sensor electrodes arranged in rows on a common surface or plane. The input device may include a plurality of sensor modules coupled to the sensor electrodes that measure capacitive sensing signals corresponding to the electrodes. Instead of measuring sensor electrodes that are in the same column, the embodiments herein simultaneously measure capacitive sensing signals on at least two sensor electrodes that are in the same row. In one example, the sensor electrodes in the row being measured are spaced the same distance from a side of a substrate coupling the electrodes to the sensor modules and may have approximately the same electrical time constant.

公开(公告)号：US20180129574A1

公开(公告)日：2018-05-10

申请号：US15863350

申请日：2018-01-05

Applicant: Huawei Technologies Co., Ltd.

Inventor： Fei Zhang ,  Defu Liao ,  Zhangping Ma

IPC: G06F11/20 ,  G06F13/42 ,  G06F13/40 ,  G06F9/50

CPC classification number: G06F11/2028 ,  G06F9/5027 ,  G06F11/1425 ,  G06F11/1428 ,  G06F11/20 ,  G06F11/2041 ,  G06F11/2097 ,  G06F13/4081 ,  G06F13/4282 ,  G06F2201/805

Abstract: A central processing unit (CPU) hot-remove method, including determining, by a controller of a server that has a non-full mesh first CPU topology comprising multiple CPUs, a first CPU of the multiple CPUs to be removed from the first CPU topology according to first indication information, determining at least one second CPU associated in the first CPU topology with the first CPU, where the at least one second CPU and the first CPU meet a preset condition associated with a relationship between the first CPU and the at least one second CPU, and sending second indication information to the first CPU topology, the second indication information instructing the first CPU topology to remove the first CPU and the at least one second CPU, resulting in a second CPU topology without the first CPU and other than the at least one second CPU.

公开(公告)号：US09819542B2

公开(公告)日：2017-11-14

申请号：US14752778

申请日：2015-06-26

Applicant: Microsoft Technology Licensing, LLC

Inventor： Douglas C. Burger

IPC: H04L12/24 ,  G06F11/14 ,  G06F11/07 ,  G06F11/30

CPC classification number: H04L41/0816 ,  G06F11/00 ,  G06F11/0709 ,  G06F11/0793 ,  G06F11/1428 ,  G06F11/3003

Abstract: Aspects extend to methods, systems, and computer program products for (re)configuring acceleration components over a network. (Re)configuration can be implemented for any of a variety of reasons, including to address an error in functionality at the acceleration component or to update functionality at the acceleration component. During (re)configuration, connectivity can be maintained for any other functionality at the acceleration component untouched by the (re)configuration. Network (re)configuration of acceleration components facilitates management of acceleration components and accelerated services from a centralized service. Network (re)configuration of acceleration components also relieves host components from having to store (potentially diverse and numerous) image files.