公开(公告)号：US20170048987A1

公开(公告)日：2017-02-16

申请号：US15338860

申请日：2016-10-31

Applicant: DAI NIPPON PRINTING CO., LTD.

Inventor： Yoichi MIURA ,  Tsuyoshi YAMAZAKI

IPC: H05K3/46 ,  G11B5/48 ,  H05K3/28 ,  H05K1/02 ,  H05K1/05

CPC classification number: H05K3/4644 ,  G11B5/48 ,  G11B5/4826 ,  G11B5/4833 ,  G11B5/49 ,  H05K1/0271 ,  H05K1/0298 ,  H05K1/05 ,  H05K1/056 ,  H05K3/28 ,  H05K2201/0394 ,  H05K2201/09081 ,  H05K2201/09781 ,  Y10T428/1171 ,  Y10T428/1179 ,  Y10T428/1193

Abstract: The present invention provides a substrate for suspension that includes a first structural part including a metal supporting substrate, an insulating layer, a wiring layer, and a cover layer, and a second structural part formed so as to extend continuously from the first structural part and has no metal supporting substrate. A position of an edge of an upper surface of the insulating layer coincides with a position of an edge of the lower surface of the cover layer or the position of the edge of the upper surface of the insulating layer is positioned on a side closer to the wiring layer than to the position of the edge of the lower surface of the cover layer at a boundary region between the first structural part and the second structural part.

Abstract translation: 本发明提供了一种悬架用基板，其具备包括金属支撑基板，绝缘层，布线层和覆盖层的第一结构部件和形成为从第一结构部件连续延伸的第二结构部件， 没有金属支撑基板。 绝缘层的上表面的边缘的位置与覆盖层的下表面的边缘的位置一致，或者绝缘层的上表面的边缘的位置位于靠近 布线层比在第一结构部分和第二结构部分之间的边界区域处的覆盖层的下表面的边缘的位置。

公开(公告)号：US20170033425A1

公开(公告)日：2017-02-02

申请号：US15195090

申请日：2016-06-28

Applicant: Intel Corporation

Inventor： Ruihua Ding ,  Min Wang ,  Mo Liu

IPC: H01P3/08 ,  H01P11/00 ,  H05K1/02

CPC classification number: H05K1/0245 ,  H01P1/203 ,  H01P3/026 ,  H01P3/04 ,  H01P3/08 ,  H01P11/003 ,  H04B3/32 ,  H05K1/0216 ,  H05K1/0228 ,  H05K3/10 ,  H05K2201/09236 ,  H05K2201/09781 ,  Y10T29/49155

Abstract: This disclosure relates generally to an electronic assembly and method having a first electrical connection point and a second electrical connection point and a differential interconnect coupling the first electrical connection point to the second electrical connection point, the differential interconnect including first and second transmission traces including a interior edges and a exterior edges opposite the interior edges, the second interior edge facing the first interior edge, and stub traces, each stub trace coupled to one of the first and second transmission traces and projecting from one of the first interior edge, the first exterior edge, the second interior edge, and the second exterior edge. A substantially equal number of stub traces project from the first exterior edge and the second exterior edge. At least twice as many stub traces project from the first and second exterior edges as project from the first and second interior edges.

Abstract translation: 本公开总体上涉及一种具有第一电连接点和第二电连接点的电子组件和方法，以及将第一电连接点耦合到第二电连接点的差分互连，差动互连包括第一和第二传输迹线，包括 内部边缘和与内部边缘相对的外部边缘，面向第一内部边缘的第二内部边缘和短截线迹线，每个短截线迹线耦合到第一和第二传输轨迹中的一个并从第一内部边缘中的一个突出，第一内部边缘 外部边缘，第二内部边缘和第二外部边缘。 从第一外边缘和第二外边缘突出的基本相等数量的短截线迹。 从第一和第二内部边缘起，从第一和第二外部边缘突出的短截线迹线的至少两倍。

公开(公告)号：US09560742B2

公开(公告)日：2017-01-31

申请号：US14580756

申请日：2014-12-23

Applicant: ALCATEL-LUCENT CANADA, INC.

Inventor： Paul J. Brown ,  Alex L. Chan

IPC: H05K1/11 ,  H05K1/02 ,  H05K3/46 ,  G06F17/50 ,  H05K3/42 ,  H05K3/00

CPC classification number: H05K1/0251 ,  G06F17/5077 ,  H05K1/0271 ,  H05K1/0298 ,  H05K1/112 ,  H05K3/0047 ,  H05K3/429 ,  H05K3/4644 ,  H05K2201/09454 ,  H05K2201/09781 ,  H05K2203/0207

Abstract: Disclosed is a printed circuit board (PCB) having backdrill reliability anchors comprising nonfunctional pads to provide mechanical reinforcement for signal pads on backdrilled plated through hole (PTH) vias, as well as associated method and machine readable storage medium.

Abstract translation: 公开了一种印刷电路板（PCB），其具有包括非功能焊盘的反向钻孔可靠性锚，以提供用于背部钻孔电镀通孔（PTH）通孔上的信号焊盘的机械加强，以及相关联的方法和机器可读存储介质。

公开(公告)号：US09532461B2

公开(公告)日：2016-12-27

申请号：US14224712

申请日：2014-03-25

Applicant: TDK CORPORATION

Inventor： Naozumi Ishikawa ,  Fumio Watanabe ,  Hiroshi Kamiyama

IPC: G03B27/68 ,  H05K3/00 ,  H05K1/02 ,  H05K1/16

CPC classification number: H05K3/0008 ,  H05K1/0269 ,  H05K1/165 ,  H05K3/0002 ,  H05K2201/09781 ,  H05K2201/09918 ,  H05K2203/056 ,  H05K2203/166

Abstract: A first alignment mark is given to a substrate, and a second alignment mark is given to a mask. The mask forms an electronic circuit pattern on the substrate. A control unit performs alignment of the mask and the substrate based on the first and second alignment marks. The second alignment mark is formed to surround the first alignment mark. The second alignment mark has a step pattern therein.

Abstract translation: 向基板施加第一对准标记，向掩模施加第二对准标记。 掩模在基板上形成电子电路图案。 控制单元基于第一和第二对准标记执行掩模和基板的对准。 第二对准标记形成为围绕第一对准标记。 第二对准标记中具有台阶图案。

公开(公告)号：US20160330844A1

公开(公告)日：2016-11-10

申请号：US15214680

申请日：2016-07-20

Applicant: Murata Manufacturing Co., Ltd.

Inventor： Yoshihito OTSUBO

IPC: H05K1/18

CPC classification number: H05K1/185 ,  H05K3/4611 ,  H05K2201/09781 ,  H05K2201/2009

Abstract: A multilayer substrate comprises: a stack having a plurality of insulating base materials; a first component arranged within the stack at a first level in a thickness direction of the stack; a second component arranged within the stack at a second level different from the first level and arranged so that, in a plan view, at least a portion of the second component overlaps with a portion of the first component; and a supplementary member arranged to at least partly exist in a range, in a thickness direction, as high as or higher than a lower end of the second component and as high as or lower than an upper end of the second component, and in a plan view, within a region of a projected area of the first component not overlapped with the second component, the supplementary member having a rigidness higher than the insulating base materials.

Abstract translation: 多层基板包括：具有多个绝缘基材的堆叠; 布置在所述堆叠内的所述堆叠的厚度方向上的第一层的第一部件; 布置在所述堆叠内的第二组件处于与所述第一水平不同的第二水平并且被布置成使得在俯视图中，所述第二部件的至少一部分与所述第一部件的一部分重叠; 以及辅助构件，其被配置为至少部分地存在于厚度方向上的高度或高于第二构件的下端的高度或高于第二构件的上端的范围内，并且在 平面图，在第一部件的投影区域的区域内不与第二部件重叠，辅助部件具有比绝缘基材高的刚性。

公开(公告)号：US20160320706A1

公开(公告)日：2016-11-03

申请号：US15189311

申请日：2016-06-22

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Chin-Hsiung HSU ,  Huang-Yu CHEN ,  Tsong-Hua OU ,  Wen-Hao CHEN

IPC: G03F7/20 ,  G06F17/50 ,  G03F1/70 ,  H01L21/3213

CPC classification number: G03F7/2022 ,  G03F1/70 ,  G06F17/5068 ,  H01L21/3213 ,  H05K3/0005 ,  H05K3/0082 ,  H05K3/06 ,  H05K3/068 ,  H05K2201/09781 ,  H05K2203/0557 ,  H05K2203/1476 ,  Y10T29/49156

Abstract: A method includes patterning a layer over a substrate with a first metal pattern; using a cut mask in a first position relative to the substrate to perform a first cut patterning for removing material from a first region within the first pattern; and using the same cut mask to perform a second cut patterning while in a second position relative to the same layer over the substrate, for removing material from a second region in a second metal pattern of the same layer over the substrate.

Abstract translation: 一种方法包括用第一金属图案在衬底上图案化层; 在相对于所述基板的第一位置使用切割掩模，以执行用于从所述第一图案内的第一区域去除材料的第一切割图案; 并且使用相同的切割掩模在相对于衬底上的相同层的第二位置执行第二切割图案，用于从衬底上的相同层的第二金属图案中的第二区域去除材料。

公开(公告)号：US09474150B2

公开(公告)日：2016-10-18

申请号：US14264756

申请日：2014-04-29

Applicant: TDK Corporation

Inventor： Bouchaib Cherif

IPC: H01G5/14 ,  H05K1/02 ,  H05K1/16 ,  H01G5/16 ,  H01G5/18 ,  H01P1/203

CPC classification number: H05K1/0292 ,  H01G5/14 ,  H01G5/16 ,  H01G5/18 ,  H01P1/20336 ,  H05K1/024 ,  H05K1/025 ,  H05K1/16 ,  H05K1/162 ,  H05K2201/09727 ,  H05K2201/09781 ,  H05K2203/171

Abstract: A tunable filter design. The filter is implemented using transmission line sections as inductive and capacitive components. At least one capacitive component is a tunable capacitor. In some implementations, the tunable capacitor may be an interdigitated array of finger elements arranged so that the spacing between fingers may be adjusted. The design has a number of advantages including high capacitance for a given circuit area, small area for a given desired capacitance, mechanical stability, high self resonance frequency, and high quality factor.

Abstract translation: 可调滤波器设计。 滤波器使用传输线路段作为电感和电容分量来实现。 至少一个电容元件是可调电容器。 在一些实施方案中，可调谐电容器可以是布置成使得可以调整手指之间的间隔的指状元件的交叉指列阵列。 该设计具有许多优点，包括给定电路面积的高电容，给定期望电容的小面积，机械稳定性，高自谐振频率和高品质因数。

公开(公告)号：US09460989B2

公开(公告)日：2016-10-04

申请号：US14183188

申请日：2014-02-18

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Shih-Wei Liang ,  Kai-Chiang Wu ,  Ming-Kai Liu ,  Chia-Chun Miao ,  Chun-Lin Lu

IPC: H01L23/48 ,  H01L23/498 ,  H01L23/485 ,  G06F17/50 ,  H01L21/768 ,  H01L23/14 ,  H05K1/11 ,  H05K1/02

CPC classification number: H01L23/485 ,  G06F17/5068 ,  H01L21/76898 ,  H01L23/147 ,  H01L23/481 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/49838 ,  H01L2224/16225 ,  H01L2924/15311 ,  H05K1/0271 ,  H05K1/115 ,  H05K2201/068 ,  H05K2201/09781 ,  H05K2201/10378

Abstract: A structure includes a substrate having a plurality of balls, a semiconductor chip, and an interposer electrically connecting the substrate and the semiconductor chip. The interposer includes a first side, a second side opposite the first side, at least one first exclusion zone extending through the interposer above each ball of the plurality of balls, at least one active through via extending from the first side of the interposer to the second side of the interposer, wherein the at least one active through via is formed outside the at least one first exclusion zone and wherein no active through vias are formed within the at least one first exclusion zone, and at least one dummy through via extending from the first side of the interposer to the second side of the interposer, wherein the at least one dummy through via is formed within the at least one first exclusion zone.

Abstract translation: 一种结构包括具有多个球的衬底，半导体芯片和电连接衬底和半导体芯片的插入器。 所述插入器包括第一侧，与所述第一侧相对的第二侧，至少一个第一排除区域，所述至少一个第一排除区域延伸穿过所述多个球的每个球上方的所述插入器，至少一个主动通孔，其从所述插入件的第一侧延伸到 其中所述至少一个活性通孔形成在所述至少一个第一排除区域的外部，并且其中在所述至少一个第一排除区域内没有形成活性通孔，以及至少一个虚拟通孔， 所述插入器的第一侧到所述插入件的第二侧，其中所述至少一个虚拟通孔形成在所述至少一个第一排除区域内。

公开(公告)号：US20160254429A1

公开(公告)日：2016-09-01

申请号：US15054697

申请日：2016-02-26

Applicant: NICHIA CORPORATION

Inventor： Yasuo FUJIKAWA ,  Takuya WASA ,  Yosuke NAKAYAMA

IPC: H01L33/62 ,  H01L33/10 ,  H01L33/08

CPC classification number: H01L33/62 ,  F21K9/00 ,  F21Y2101/00 ,  F21Y2103/10 ,  F21Y2105/16 ,  F21Y2107/70 ,  F21Y2115/10 ,  H01L25/0753 ,  H01L27/156 ,  H05K1/118 ,  H05K1/141 ,  H05K3/363 ,  H05K2201/09172 ,  H05K2201/09781 ,  H05K2201/10106

Abstract: A light emitting device includes a first substrate including a flexible first base member and a first wiring pattern provided on the first base member; a second substrate including a second base member and a second wiring pattern provided on the second base member; and a plurality of light emitting elements mounted on the first wiring pattern. The first substrate includes: a joining end portion that is located at a first, joining end of the first substrate, and that overlaps a portion of the second substrate, and a second end, other than the joining end, that does not overlap the second substrate. The first wiring pattern and the second wiring pattern do not face each other. An electrically conductive joining member is disposed across the first wiring pattern and the second wiring pattern, while partially covering the joining end portion of the first substrate.

Abstract translation: 发光器件包括：第一基板，包括柔性第一基底部件和设置在第一基底部件上的第一布线图案; 第二基板，包括设置在所述第二基底构件上的第二基底构件和第二布线图案; 以及安装在第一布线图案上的多个发光元件。 所述第一基板包括：接合端部，其位于所述第一基板的第一接合端，并且与所述第二基板的一部分重叠，以及与所述接合端不同的第二端， 基质。 第一布线图案和第二布线图案不相对。 在第一布线图案和第二布线图案的两侧设置导电性接合构件，同时部分地覆盖第一基板的接合端部。

公开(公告)号：US09433078B2

公开(公告)日：2016-08-30

申请号：US13673986

申请日：2012-11-09

Applicant: SANMINA CORPORATION

Inventor： Vladimir Duvanenko

IPC: H05K1/16 ,  H05K1/02 ,  H05K1/18 ,  H05K3/00 ,  H05K1/11

CPC classification number: H05K1/0216 ,  H05K1/0245 ,  H05K1/0251 ,  H05K1/116 ,  H05K1/182 ,  H05K3/00 ,  H05K2201/09781 ,  Y10T29/49146

Abstract: A printed circuit board (PCB) is provided comprising a plurality of non-conductive layers with conductive or signal layers in between. The PCB includes a first conductive via traversing the plurality of non-conductive and conductive or signal layers as well as a second conductive via traversing the plurality of non-conductive layers and conductive or signal layers, the second conductive via located substantially parallel to the first conductive via. An embedded electro-optical passive element is also provided that extends perpendicular to and between the first conductive via and the second conductive via. The electro-optical passive element embedded is located within a selected layer at a first depth in the printed circuit board, wherein such first depth is selected to reflect an incident electromagnetic wave back into the printed circuit board to enhance or diminish an electrical signal in the first conductive via by creating a positive or negative electromagnetic interference.

Abstract translation: 提供了一种印刷电路板（PCB），包括多个非导电层，其间具有导电层或信号层。 PCB包括穿过多个非导电和导电或信号层的第一导电通孔以及穿过多个非导电层和导电层或信号层的第二导电通孔，第二导电通孔基本上平行于第一导电通孔 导电通孔。 还提供了嵌入的电光无源元件，其垂直于第一导电通孔和第二导电通孔之间延伸。 嵌入的电光无源元件位于印刷电路板的第一深度处的选定层内，其中选择这样的第一深度以将入射的电磁波反射回印刷电路板，以增强或减少印刷电路板中的电信号 通过产生正或负电磁干扰的第一导电通孔。