公开(公告)号：US08981236B2

公开(公告)日：2015-03-17

申请号：US13730874

申请日：2012-12-29

Applicant: Hong Fu Jin Precision Industry (WuHan) Co., Ltd. ,  Hon Hai Precision Industry Co., Ltd.

Inventor： Feng Zhang

IPC: H05K1/00 ,  H05K1/03 ,  H05K1/02 ,  H05K3/34

CPC classification number: H05K1/03 ,  H05K1/024 ,  H05K3/3452 ,  H05K2201/0191 ,  H05K2201/09727 ,  H05K2201/09972

Abstract: A printed circuit board includes a line intensive distribution area, a line sparse distribution area, a solder mask layer, and a signal layer. A first signal line is laid on the signal layer. The first signal line crosses the line intensive distribution area and the line sparse distribution area. The first signal line is narrower in the line intensive distribution area than in the line sparse distribution area. The solder mask layer is thicker in the line intensive distribution area than in the line sparse distribution area.

Abstract translation: 印刷电路板包括线密集分布区域，线稀疏分布区域，焊接掩模层和信号层。 第一信号线被放置在信号层上。 第一条信号线穿过线密集分布区和线稀疏分布区。 第一条信号线在线密集分布区域比线稀疏分布区域窄。 在线密集分布区域中的焊料掩模层比线稀疏分布区域更厚。

公开(公告)号：US20150041859A1

公开(公告)日：2015-02-12

申请号：US13962622

申请日：2013-08-08

Applicant: Infineon Technologies AG

Inventor： Ralf Otremba ,  Josef Höglauer

IPC: H01L23/522 ,  H01L29/778

CPC classification number: H01L23/5226 ,  H01L23/3107 ,  H01L23/49503 ,  H01L23/49541 ,  H01L23/49827 ,  H01L23/49838 ,  H01L29/2003 ,  H01L29/778 ,  H01L2224/48091 ,  H05K1/0262 ,  H05K1/181 ,  H05K2201/0761 ,  H05K2201/093 ,  H05K2201/09309 ,  H05K2201/09336 ,  H05K2201/09972 ,  H01L2924/00014

Abstract: A redistribution board includes a first conductive layer including a redistribution structure for low voltage signals, a second conductive layer including a redistribution structure for high voltage signals, and a non-conductive layer. The second conductive layer is spaced apart from the first conductive layer by the non-conductive layer. The redistribution board further includes a conductive connector extending from a mounting surface of the redistribution board to the second conductive layer. The conductive connector is surrounded by a low voltage trace of the first conductive layer.

Abstract translation: 再分配板包括：第一导电层，包括用于低电压信号的再分配结构;第二导电层，包括用于高电压信号的再分配结构;以及非导电层。 第二导电层通过非导电层与第一导电层间隔开。 再分配板还包括从再分布板的安装表面延伸到第二导电层的导电连接器。 导电连接器被第一导电层的低电压迹线围绕。

公开(公告)号：US08939604B2

公开(公告)日：2015-01-27

申请号：US13423142

申请日：2012-03-16

Applicant: Gerald Edward Briggs

Inventor： Gerald Edward Briggs

IPC: F21S9/00 ,  H01L33/48 ,  H05B37/02 ,  H05B33/08

CPC classification number: H05B33/0827 ,  F21K9/60 ,  F21K99/00 ,  F21S4/20 ,  F21V23/005 ,  F21V23/04 ,  F21Y2105/10 ,  F21Y2115/10 ,  H01L25/0753 ,  H01L33/62 ,  H01L2924/0002 ,  H05B33/0803 ,  H05B33/0845 ,  H05B33/0857 ,  H05K1/05 ,  H05K2201/09309 ,  H05K2201/09972 ,  H05K2201/10106 ,  H01L2924/00

Abstract: A LED based lighting apparatus is disclosed. The light engine used in the lighting apparatus may use a multi-layer metal core printed circuit board and have a plurality of LED groups that are independently controllable by a control unit. The power supply input and return paths connected to each LED group may be implemented on different layers to allow a compact footprint that may be used with traditional fluorescent encasements with relatively little modification.

Abstract translation: 公开了一种基于LED的照明装置。 在照明装置中使用的光引擎可以使用多层金属芯印刷电路板，并且具有可由控制单元独立控制的多个LED组。 连接到每个LED组的电源输入和返回路径可以在不同的层上实现，以允许紧凑的占地面积可以与具有相对较少修改的传统荧光灯罩一起使用。

公开(公告)号：US20150024547A1

公开(公告)日：2015-01-22

申请号：US14509939

申请日：2014-10-08

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Chuei-Tang Wang ,  Der-Chyang Yeh

IPC: H01L23/552 ,  H01L25/00 ,  H01L23/00 ,  H01L21/56 ,  H01L21/768

CPC classification number: H01L23/552 ,  H01L21/565 ,  H01L21/76802 ,  H01L21/76877 ,  H01L21/76898 ,  H01L23/3128 ,  H01L24/16 ,  H01L24/64 ,  H01L25/0655 ,  H01L25/16 ,  H01L25/50 ,  H01L2224/02317 ,  H01L2224/02372 ,  H01L2224/02373 ,  H01L2224/0401 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/16235 ,  H01L2224/81191 ,  H01L2924/12042 ,  H01L2924/15311 ,  H01L2924/181 ,  H05K3/284 ,  H05K2201/0715 ,  H05K2201/09972 ,  H05K2201/10378 ,  H05K2203/1316 ,  H01L2924/00014 ,  H01L2924/014 ,  H01L2924/00

Abstract: An integrated circuit structure includes a substrate, a photosensitive molding on a first side of the substrate, a via formed in the molding, and a conformable metallic layer deposited over the first side of the substrate and in the via. A through via may be formed through the substrate aligned with the via in the molding with an electrically conductive liner deposited in the through via in electrical contact with the conformable metallic layer. The integrated circuit structure may further include a connector element such as a solder ball on an end of the through via on a second side of the substrate opposite the first side. The integrated circuit structure may further include a die on the first side of the substrate in electrical contact with another through via or with a redistribution layer.

Abstract translation: 集成电路结构包括基板，在基板的第一侧上的感光模制件，在模制件中形成的通孔，以及沉积在基板的第一侧和通孔中的一致的金属层。 可以通过在模制件中与通孔对准的基板形成贯通孔，其中导电衬垫沉积在贯通通孔中，以与适形金属层电接触。 集成电路结构还可以包括诸如焊球之间的连接器元件，该连接器元件在通孔的端部上，与第一侧相反的第二面上。 集成电路结构还可以包括在基板的第一侧上的与另一通孔或再分布层电接触的管芯。

公开(公告)号：US20140321071A1

公开(公告)日：2014-10-30

申请号：US14054308

申请日：2013-10-15

Applicant: Samsung Display Co., Ltd.

Inventor： You Bean KIM ,  Seock-Hwan KANG ,  Jong Seo LEE

IPC: H05K1/02 ,  H05K3/46

CPC classification number: H05K1/0298 ,  H05K1/024 ,  H05K2201/0195 ,  H05K2201/09972

Abstract: A printed circuit board includes an insulation layer adjacent to a high-speed signal wire layer. A low-loss material layer is provided between the high-speed signal wire layer and the insulation layer. As a result, it is possible to reduce frequency loss of a high-speed signal wire layer and improve reliability of the printed circuit board.

Abstract translation: 印刷电路板包括与高速信号线层相邻的绝缘层。 在高速信号线层和绝缘层之间设置低损耗材料层。 结果，可以减少高速信号线层的频率损失并提高印刷电路板的可靠性。

公开(公告)号：US20140300375A1

公开(公告)日：2014-10-09

申请号：US14350808

申请日：2012-11-19

Applicant: FUJI ELECTRIC CO., LTD.

Inventor： Masami Kishiro

IPC: G01R27/26 ,  G01P15/00

CPC classification number: G01R27/2605 ,  G01D5/2417 ,  G01P15/00 ,  G01P15/125 ,  G01P2015/082 ,  G01P2015/084 ,  H05K1/0256 ,  H05K3/3452 ,  H05K2201/09972 ,  H05K2201/10151

Abstract: A capacitance detection circuit has at least a carrier signal generating circuit that supplies a carrier signal to one of a movable or a fixed electrode of a sensor, an operational amplifier with one of the movable or fixed electrode as an input and ground as another input, and a printed circuit board on which the physical quantity sensor, the carrier signal generating circuit, and the operational amplifier are mounted. An insulation-secured area on the printed circuit board is configured as a moisture absorption reduction area, including at least an electrode connection part of the physical quantity sensor, an input-side connection part of the operational amplifier, and a connection part connected to the input side of the operational amplifier out of connection parts of input-side circuit components connected between the electrode connection part and the input-side connection part.

Abstract translation: 电容检测电路至少具有载波信号发生电路，其将载波信号提供给传感器的可移动或固定电极中的一个，可移动或固定电极之一作为输入的运算放大器作为另一输入， 以及其上安装有物理量传感器，载波信号发生电路和运算放大器的印刷电路板。 印刷电路板上的绝缘保护区域被构造为吸湿减少区域，该区域至少包括物理量传感器的电极连接部分，运算放大器的输入侧连接部分和连接部分 连接在电极连接部和输入侧连接部之间的输入侧电路部件的连接部分的运算放大器的输入侧。

公开(公告)号：US08847574B2

公开(公告)日：2014-09-30

申请号：US13498086

申请日：2010-09-23

Applicant: Iain Barnett ,  Jonathan Ephraim David Hurwitz ,  William Michael James Holland

Inventor： Iain Barnett ,  Jonathan Ephraim David Hurwitz ,  William Michael James Holland

IPC: H04B3/00 ,  H04B3/56

CPC classification number: H04B3/56 ,  H05K1/0256 ,  H05K1/162 ,  H05K2201/09309 ,  H05K2201/09972

Abstract: Disclosed is an electrical isolator circuit comprising an input stage comprising first and second inputs, the input stage being configured to receive an input voltage signal; an output stage comprising first and second outputs electrically connected across a load capacitor; and a DC isolator comprising a first capacitor between said first input and said first output and second capacitor between said second input and said second output. The first and second plates of each of the first, second and load capacitors are defined by conductive layers of a printed circuit board and the dielectric of each of the first, second and load capacitors are defined by a non-conducting part of the printed circuit board.

Abstract translation: 公开了一种电气隔离器电路，包括具有第一和第二输入的输入级，输入级被配置为接收输入电压信号; 输出级包括跨过负载电容器电连接的第一和第二输出; 以及直流隔离器，其包括在所述第一输入和所述第一输出之间的第一电容器和在所述第二输入和所述第二输出之间的第二电容器。 第一，第二和负载电容器中的每一个的第一和第二板由印刷电路板的导电层限定，并且第一，第二和负载电容器中的每一个的电介质由印刷电路的不导电部分限定 板。

公开(公告)号：US20140203454A1

公开(公告)日：2014-07-24

申请号：US14224166

申请日：2014-03-25

Applicant: Murata Manufacturing Co., Ltd.

Inventor： Shigeru TAGO ,  Noboru KATO

IPC: H01L25/065 ,  H01L23/48

CPC classification number: H01L25/0657 ,  H01L23/3114 ,  H01L23/481 ,  H01L23/49827 ,  H01L23/525 ,  H01L23/5286 ,  H01L23/5389 ,  H01L24/20 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/06182 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/19 ,  H01L2924/00013 ,  H01L2924/19105 ,  H05K1/185 ,  H05K2201/09972 ,  H01L2224/13099 ,  H01L2224/05099 ,  H01L2224/05599

Abstract: A semiconductor device includes an analog integrated circuit and a digital integrated circuit provided on a major surface of a substrate. An analog ground terminal is provided for the analog integrated circuit, and digital ground terminals are provided for the digital integrated circuit. An analog ground layer is stacked on the substrate so as to face the analog integrated circuit, and digital ground layers are stacked on the substrate so as to face the digital integrated circuit. The analog ground terminal is connected to the analog ground layer, and the digital ground terminals are connected to the digital ground layers, respectively.

Abstract translation: 半导体器件包括设置在基板的主表面上的模拟集成电路和数字集成电路。 为模拟集成电路提供模拟接地端子，为数字集成电路提供数字接地端子。 将模拟接地层堆叠在基板上以面向模拟集成电路，并且数字接地层堆叠在基板上以面对数字集成电路。 模拟接地端子连接到模拟接地层，数字接地端子分别连接到数字接地层。

公开(公告)号：US20140160693A1

公开(公告)日：2014-06-12

申请号：US14082414

申请日：2013-11-18

Applicant: MURATA MANUFACTURING CO., LTD.

Inventor： Masashi MARUYAMA

IPC: H05K1/18

CPC classification number: H05K1/165 ,  H03F3/195 ,  H03F3/68 ,  H03F2200/111 ,  H05K1/0228 ,  H05K1/0298 ,  H05K3/4611 ,  H05K2201/09972 ,  H05K2201/10015 ,  H05K2201/1003 ,  H05K2201/10098

Abstract: A semiconductor module includes a circuit substrate, a first semiconductor device substrate that is mounted on the circuit substrate and that processes an input signal of a first frequency band, a second semiconductor device substrate that is mounted on the circuit substrate and that processes an input signal of a second frequency band, and a control device substrate that is arranged between the first and second semiconductor device substrates and that controls the first and second semiconductor device substrates.

Abstract translation: 半导体模块包括电路基板，安装在电路基板上并处理第一频带的输入信号的第一半导体器件基板，安装在电路基板上的第二半导体器件基板，并处理输入信号 以及配置在第一和第二半导体器件基板之间并控制第一和第二半导体器件基板的控制器件基板。

公开(公告)号：US08736044B2

公开(公告)日：2014-05-27

申请号：US12843680

申请日：2010-07-26

Applicant: Mudasir Ahmad ,  Kuo-Chuan Liu ,  Mohan Nagar ,  Bangalore Shanker

Inventor： Mudasir Ahmad ,  Kuo-Chuan Liu ,  Mohan Nagar ,  Bangalore Shanker

IPC: H01L23/04

CPC classification number: H01L23/3675 ,  H01L21/563 ,  H01L23/562 ,  H01L24/13 ,  H01L24/16 ,  H01L24/29 ,  H01L24/32 ,  H01L24/48 ,  H01L24/81 ,  H01L24/83 ,  H01L25/0655 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/291 ,  H01L2224/29191 ,  H01L2224/2929 ,  H01L2224/29339 ,  H01L2224/29393 ,  H01L2224/32227 ,  H01L2224/33181 ,  H01L2224/48227 ,  H01L2224/73153 ,  H01L2224/73204 ,  H01L2224/81191 ,  H01L2224/81815 ,  H01L2224/83191 ,  H01L2224/83801 ,  H01L2224/8385 ,  H01L2224/83851 ,  H01L2924/00014 ,  H01L2924/07802 ,  H01L2924/14 ,  H01L2924/1615 ,  H01L2924/16235 ,  H01L2924/16251 ,  H01L2924/163 ,  H01L2924/3511 ,  H05K1/0203 ,  H05K1/141 ,  H05K3/3436 ,  H05K2201/09972 ,  H05K2201/10371 ,  Y02P70/613 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: To minimize the warpage of an organic substrate that supports at least one electrical hardware component (e.g., a system-in-package module), a bottom surface of a lid is attached to a top surface of the electrical hardware component. The lid includes a leg that extends from the bottom surface of the lid towards a top surface of the substrate. A portion of the leg closest to the substrate may move relative to the substrate. As the lid warps, the lid does not also cause distortion of the substrate. The leg may be a flange that extends at least a portion of the width or at least a portion of the length of the lid, may be a post located at the perimeter of the lid, or may be any other portion extending from above the electrical component towards the substrate.

Abstract translation: 为了最小化支持至少一个电气硬件部件（例如，系统级封装模块）的有机基板的翘曲，盖的底表面附接到电气硬件部件的顶表面。 盖子包括从盖的底表面朝向衬底的顶表面延伸的腿部。 最靠近基底的腿的一部分可以相对于基底移动。 当盖子翘曲时，盖子也不会引起基板的变形。 该腿部可以是延伸至该宽度的至少一部分的凸缘或该盖的长度的至少一部分，该凸缘可以是位于盖的周边的柱，或者可以是从上方延伸的任何其它部分 元件朝向基板。