公开(公告)号：US20200287551A1

公开(公告)日：2020-09-10

申请号：US16291286

申请日：2019-03-04

Applicant: Xilinx, Inc.

Inventor： Mayank Raj ,  Didem Z. Turker Melek ,  Parag Upadhyaya ,  Yohan Frans ,  Kun-Yung Chang

IPC: H03L1/02 ,  H03L7/099 ,  H03L7/093

Abstract: A phase locked loop (PLL) circuit includes a voltage controlled oscillator (VCO), a first loop circuit, and a second loop circuit. The first loop circuit includes a first loop filter configured to receive a first signal based on a feedback signal from the VCO and provide a first VCO frequency control signal to the VCO. The second loop circuit includes a compensation circuit configured to receive a reference signal and the first signal, and provide a second VCO frequency control signal to the VCO.

公开(公告)号：US10763864B2

公开(公告)日：2020-09-01

申请号：US16145782

申请日：2018-09-28

Applicant: NXP USA, INC.

Inventor： Birama Goumballa ,  Pierre Savary ,  Cristian Pavao Moreira

IPC: H03L1/02 ,  G01S7/03 ,  H03L7/099 ,  H03L7/089

Abstract: The disclosure relates to voltage-controlled-oscillator circuit comprising: a charge-pump configured to generate a tuning-voltage, the tuning-voltage having a minimum-operating-voltage; an offset-voltage-source configured to generate an offset-voltage in accordance with the minimum-operating-voltage; and a voltage-controlled-oscillator, VCO, configured to provide an oscillator frequency in accordance with the tuning-voltage and the offset-voltage.

公开(公告)号：US10742197B2

公开(公告)日：2020-08-11

申请号：US16200975

申请日：2018-11-27

Applicant: STMicroelectronics Asia Pacific Pte Ltd

Inventor： Li Cai ,  Yannick Guedon ,  Hugo Gicquel

IPC: H03K3/011 ,  H03K3/03 ,  H03L1/02 ,  G05F3/24

Abstract: An oscillator circuit includes a first current generator circuit that generates a current complementary to absolute temperature and a second current generator that generates a current proportional to absolute temperature. A temperature slope control circuit adjusts slopes of the current complementary to absolute temperature and the current proportional to absolute temperature in a complementary fashion and adds the current complementary to absolute temperature to the current proportional to absolute temperature after slope control to produce a temperature independent current. A current control circuit adjusts magnitude of the temperature independent current to produce a magnitude adjusted temperature independent current. A current controlled oscillator generates an output signal as a function of the magnitude adjusted temperature independent current.

公开(公告)号：US20200177188A1

公开(公告)日：2020-06-04

申请号：US16682824

申请日：2019-11-13

Applicant: ABLIC Inc.

Inventor： Toshiyuki TANAKA

IPC: H03L1/02 ,  H03K3/0231 ,  H03K3/011 ,  G06F1/06

Abstract: Provided is a relaxation oscillator that is very small in temperature deviation of an oscillation period. The relaxation oscillator includes an oscillation circuit, a variable frequency divider, and a counter. The oscillation circuit is configured to switch between a first clock signal having a negative value as a first-order temperature coefficient of an oscillation period, and a second clock signal having a positive value as a first-order temperature coefficient of an oscillation period, based on a signal from the counter, and to output the switched-to clock signal as a third clock signal. The variable frequency divider is configured to divide the frequency of the third clock signal that is output from the oscillation circuit, and to output the frequency-divided third clock signal as a clock signal. The counter is reset by the clock signal.

公开(公告)号：US10651855B2

公开(公告)日：2020-05-12

申请号：US15614923

申请日：2017-06-06

Applicant: SEIKO EPSON CORPORATION

Inventor： Takayuki Kikuchi

IPC: H03L1/04 ,  H03H9/10 ,  H03H9/05 ,  G05D23/19 ,  G01K7/02 ,  H03L1/02 ,  G01K7/16

Abstract: An oscillator includes a container, an oscillation element housed in the container, a heating circuit housed in the container, and adapted to control a temperature of the oscillation element, a temperature detection circuit housed in the container, a temperature control circuit housed in the container, and adapted to control the heating circuit based on an output of the temperature detection circuit, at least one connecting wire housed in the container, and electrically connects a ground of the temperature detection circuit and a ground of the temperature control circuit to each other, and a ground external terminal disposed on an outer surface of the container, and electrically connected to the ground of the temperature detection circuit and the ground of the temperature control circuit.

公开(公告)号：US10608650B2

公开(公告)日：2020-03-31

申请号：US16002881

申请日：2018-06-07

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Arlo James Aude ,  Soumya Chandramouli ,  Roland Nii Ofei Ribeiro ,  Abishek Manian

IPC: H03B5/04 ,  H03B5/12 ,  H03L1/02 ,  H03L7/099 ,  H02M3/07

Abstract: In examples, a voltage-controlled oscillator (VCO) comprises an inductor; a first pair of transistors having first terminals coupled to a voltage source, second terminals coupled to opposing ends of the inductor, and control terminals coupled to opposing ends of the inductor; and a second pair of transistors having first terminals coupled to ground, second terminals coupled to opposing ends of the inductor, and control terminals coupled to opposing ends of the inductor. The VCO also comprises a first transistor coupled to at least one capacitor, the combination of the first transistor and the at least one capacitor coupled to the inductor in parallel. The VCO further comprises second, third, and fourth transistors coupled to a control terminal of the first transistor, the second transistor coupled to the voltage source, the fourth transistor coupled to ground, and the third transistor configured to receive a ramped voltage.

公开(公告)号：US20200052704A1

公开(公告)日：2020-02-13

申请号：US16538569

申请日：2019-08-12

Applicant: Eta Compute, Inc.

Inventor： Gopal Raghavan

IPC: H03L1/02 ,  H03H9/19 ,  G06F1/14 ,  G06F1/08 ,  G06N3/08

Abstract: Temperature-independent clock generation systems and methods are described that include a trained neural network coupled to a frequency correction circuit that corrects a crystal resonator output of a clock signal having a frequency that changes with changes in temperature. The neural network is trained with test temperatures and corresponding temperature based changes in frequency for test resonators of the same type as the resonator of the real time clock. The neutral network is trained to output frequency corrections based on a set of measured reference temperature-based changes in frequency for the crystal resonator and a current temperature of the resonator. The frequency correction circuit receives the frequency corrections from the neural network and corrects changes in the frequency caused by the changes in temperature of the resonator to provide a clock signal having an output frequency that is independent of the current temperature of the resonator.

公开(公告)号：US10530372B1

公开(公告)日：2020-01-07

申请号：US15470616

申请日：2017-03-27

Applicant: MY Tech, LLC

Inventor： Tommy Yu ,  Avanindra Madisetti

IPC: H03L7/085 ,  H03L7/10 ,  H03L7/099 ,  H03B21/02 ,  H04J3/06 ,  G04F5/04 ,  H03L1/02 ,  H03L7/06

Abstract: Systems and methods for digital synthesis of an output signal using a frequency generated from a resonator and computing amplitude values that take into account temperature variations and resonant frequency variations resulting from manufacturing variability are described. A direct frequency synthesizer architecture is leveraged on a high Q resonator, such as a film bulk acoustic resonator (FBAR), a spectral multiband resonator (SMR), and a contour mode resonator (CMR) and is used to generate pristine signals.

公开(公告)号：US10530299B2

公开(公告)日：2020-01-07

申请号：US15412913

申请日：2017-01-23

Applicant: SEIKO EPSON CORPORATION

Inventor： Takayuki Kikuchi

IPC: H03H9/10 ,  H03B5/32 ,  H03H3/02 ,  H03H9/13 ,  H03H9/19 ,  H03L1/02 ,  H03H9/02 ,  H03H9/05

Abstract: A resonator element includes an SC-cut quartz crystal substrate having a thickness t, and an excitation electrode disposed on a principal surface of the quartz crystal substrate, the principal surface being square or rectangular in shape, a side of which has a length L, 28≤L/t≤60 is satisfied.

公开(公告)号：US20200005729A1

公开(公告)日：2020-01-02

申请号：US16022357

申请日：2018-06-28

Applicant: Intel Corporation

Inventor： Christopher Mozak ,  Senthil Kumar Sampath

IPC: G09G5/00 ,  H03K5/135 ,  H03K5/14 ,  H03L1/00 ,  H03L7/081 ,  H03L1/02

Abstract: Techniques and mechanisms for determining a delay to be applied to a clock signal for synchronizing data communication. In an embodiment, a delay is applied to a first clock signal to generate a second clock signal, which is then communicated to a latch circuit via a clock signal distribution path. The delay is determined based on an evaluation of a first time needed for signal communication via a model of the clock signal distribution path. Such determining is further based on an evaluation of a second time for one cycle of a cyclical signal, where said cycle correspond to that of the first clock signal. In another embodiment, multiple different delays are applied each to a different respective clock signal, where each of said delays is based on both the evaluation of the first time and the evaluation of the second time.