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公开(公告)号：US11670615B2
公开(公告)日：2023-06-06
申请号：US17131588
申请日：2020-12-22
Inventor： Liang Wang , Rajesh Katkar , Javier A. DeLaCruz , Arkalgud R. Sitaram
IPC: H01L23/00 , H01L23/498 , H01L23/532 , H01L23/528 , H01L23/10 , B81C1/00 , H05K1/11
CPC classification number: H01L24/29 , B81C1/00269 , B81C1/00293 , H01L23/10 , H01L23/49838 , H01L23/528 , H01L23/53228 , H01L23/53242 , H01L24/05 , H01L24/06 , H01L24/08 , B81B2207/012 , B81C2203/035 , H01L23/562 , H01L24/80 , H01L2224/05551 , H01L2224/05552 , H01L2224/05555 , H01L2224/05571 , H01L2224/05647 , H01L2224/05686 , H01L2224/06135 , H01L2224/06155 , H01L2224/06165 , H01L2224/06505 , H01L2224/08121 , H01L2224/08237 , H01L2224/29019 , H01L2224/8001 , H01L2224/80047 , H01L2224/80895 , H01L2224/80896 , H01L2224/80948 , H05K1/111 , H01L2224/05552 , H01L2924/00012 , H01L2224/05647 , H01L2924/00014 , H01L2224/05686 , H01L2924/053
Abstract: A bonded structure can include a first element having a first conductive interface feature and a second element having a second conductive interface feature. An integrated device can be coupled to or formed with the first element or the second element. The first conductive interface feature can be directly bonded to the second conductive interface feature to define an interface structure. The interface structure can be disposed about the integrated device in an at least partially annular profile to connect the first and second elements.
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公开(公告)号：US11658173B2
公开(公告)日：2023-05-23
申请号：US17131329
申请日：2020-12-22
Inventor： Cyprian Emeka Uzoh , Arkalgud R. Sitaram , Paul Enquist
IPC: H01L25/00 , H01L23/31 , H01L21/56 , H01L21/304 , H01L21/306 , H01L21/308 , H01L21/683 , H01L25/065
CPC classification number: H01L25/50 , H01L21/304 , H01L21/306 , H01L21/3081 , H01L21/561 , H01L21/683 , H01L23/3121 , H01L23/3135 , H01L25/0657 , H01L2225/06513 , H01L2225/06541 , H01L2924/1304 , H01L2924/1434 , H01L2924/1461 , H01L2924/351 , H01L2924/3511 , H01L2924/3511 , H01L2924/00 , H01L2924/1434 , H01L2924/00012 , H01L2924/1461 , H01L2924/00012 , H01L2924/1304 , H01L2924/00012
Abstract: In various embodiments, a method for forming a bonded structure is disclosed. The method can comprise mounting a first integrated device die to a carrier. After mounting, the first integrated device die can be thinned. The method can include providing a first layer on an exposed surface of the first integrated device die. At least a portion of the first layer can be removed. A second integrated device die can be directly bonded to the first integrated device die without an intervening adhesive.
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公开(公告)号：US20230130580A1
公开(公告)日：2023-04-27
申请号：US18145282
申请日：2022-12-22
Inventor： Cyprian Emeka Uzoh , Arkalgud R. Sitaram , Paul Enquist
IPC: H01L25/00 , H01L23/31 , H01L21/56 , H01L21/304 , H01L21/306 , H01L21/308 , H01L21/683 , H01L25/065
Abstract: In various embodiments, a method for forming a bonded structure is disclosed. The method can comprise mounting a first integrated device die to a carrier. After mounting, the first integrated device die can be thinned. The method can include providing a first layer on an exposed surface of the first integrated device die. At least a portion of the first layer can be removed. A second integrated device die can be directly bonded to the first integrated device die without an intervening adhesive.
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公开(公告)号：US20230123423A1
公开(公告)日：2023-04-20
申请号：US18047238
申请日：2022-10-17
Applicant: ADEIA SEMICONDUCTOR BONDING TECHNOLOGIES INC
Inventor： Guilian Gao , Gaius Gillman Fountain, Jr. , Belgacem Haba , Rajesh Katkar
IPC: H01L23/522 , H01L25/065 , H01L23/00 , H01L23/48
Abstract: Microelectronic devices having stacked electromagnetic coils are disclosed. In one example, a microelectronic device can include a first semiconductor element and a second semiconductor element disposed on the first semiconductor element. The microelectronic device can also include an electromagnetic coil. A first portion of the electromagnetic coil and a second portion of the electromagnetic coil may be spaced apart by the first semiconductor element. A first conductive via extending through the first semiconductor element may connect the first and second portions of the electromagnetic coil. Methods for forming such microelectronic devices are also disclosed.
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公开(公告)号：US20230115122A1
公开(公告)日：2023-04-13
申请号：US17931826
申请日：2022-09-13
Inventor： Cyprian Emeka Uzoh , Thomas Workman , Gabriel Z. Guevara , Dominik Suwito , Guilian Gao
IPC: H01L21/762 , H01L21/786 , H01L21/321 , H01L21/02
Abstract: Methods of bonding thin dies to substrates. In one such method, a wafer is attached to a support layer. The wafer and support layer are attached to a dicing structure and then singulated to form a plurality of semiconductor die components. Each semiconductor die component comprises a thinned die and a support layer section attached to the thinned die where each support layer section is disposed between the corresponding thinned die and the dicing structure. At least one of the semiconductor die components is then bonded to a substrate without an intervening adhesive such that the thinned die is disposed between the substrate and the support layer section. The support layer section is then removed from the thinned die.
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Patent Agency Ranking
公开(公告)号：US11538781B2
公开(公告)日：2022-12-27
申请号：US17646238
申请日：2021-12-28
Inventor： Belgacem Haba
Abstract: In one embodiment, an integrated device package is disclosed. The integrated device package can comprise a carrier an a molding compound over a portion of an upper surface of the carrier. The integrated device package can comprise an integrated device die mounted to the carrier and at least partially embedded in the molding compound, the integrated device die comprising active circuitry. The integrated device package can comprise a stress compensation element mounted to the carrier and at least partially embedded in the molding compound, the stress compensation element spaced apart from the integrated device die, the stress compensation element comprising a dummy stress compensation element devoid of active circuitry. At least one of the stress compensation element and the integrated device die can be directly bonded to the carrier without an adhesive.
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公开(公告)号：US20250149510A1
公开(公告)日：2025-05-08
申请号：US19013905
申请日：2025-01-08
Inventor： Paul M. Enquist , Gaius Gillman Fountain, JR.
IPC: H01L25/065 , H01L21/20 , H01L21/683 , H01L21/768 , H01L23/00 , H01L23/498 , H01L25/00 , H10D1/47 , H10D88/00
Abstract: A method of integrating a first substrate having a first surface with a first insulating material and a first contact structure with a second substrate having a second surface with a second insulating material and a second contact structure. The first insulating material is directly bonded to the second insulating material. A portion of the first substrate is removed to leave a remaining portion. A third substrate having a coefficient of thermal expansion (CTE) substantially the same as a CTE of the first substrate is bonded to the remaining portion. The bonded substrates are heated to facilitate electrical contact between the first and second contact structures. The third substrate is removed after heating to provided a bonded structure with reliable electrical contacts.
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48.发明授权公开(公告)号：US12272677B2
公开(公告)日：2025-04-08
申请号：US18589231
申请日：2024-02-27
Inventor： Cyprian Emeka Uzoh , Rajesh Katkar , Thomas Workman , Guilian Gao , Gaius Gillman Fountain, Jr. , Laura Wills Mirkarimi , Belgacem Haba , Gabriel Z. Guevara , Joy Watanabe
IPC: H01L21/56 , H01L23/00 , H01L23/31 , H01L25/065
Abstract: Direct bonded stack structures for increased reliability and improved yields in microelectronics are provided. Structural features and stack configurations are provided for memory modules and 3DICs to reduce defects in vertically stacked dies. Example processes alleviate warpage stresses between a thicker top die and direct bonded dies beneath it, for example. An etched surface on the top die may relieve warpage stresses. An example stack may include a compliant layer between dies. Another stack configuration replaces the top die with a layer of molding material to circumvent warpage stresses. An array of cavities on a bonding surface can alleviate stress forces. One or more stress balancing layers may also be created on a side of the top die or between other dies to alleviate or counter warpage. Rounding of edges can prevent stresses and pressure forces from being destructively transmitted through die and substrate layers. These measures may be applied together or in combinations in a single package.
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公开(公告)号：US20250113700A1
公开(公告)日：2025-04-03
申请号：US18532332
申请日：2023-12-07
Inventor： Rajesh Katkar , Belgacem Haba , Cyprian Emeka Uzoh
Abstract: Conductive features of a device including quantum dots of a first substrate are bonded to conductive features of a second substrate. A quantum dot layer is formed on the first substrate having conductive features in a dielectric layer. Hybrid bonding of the first substrate to the second substrate is performed without use of an intervening adhesive to connect the first conductive features and the second conductive features.
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公开(公告)号：US12261099B2
公开(公告)日：2025-03-25
申请号：US18394985
申请日：2023-12-22
Inventor： Guilian Gao , Belgacem Haba , Laura Mirkarimi
IPC: H01L23/46 , H01L23/00 , H01L23/053 , H01L23/38
Abstract: In some implementations, a device package may include a package substrate, a package cover disposed on the package substrate, and an integrated cooling assembly disposed between the package substrate and the package cover. The integrated cooling assembly may include a semiconductor device and a cold plate having a first side attached to the semiconductor device and a second side opposite the first side. An adhesive layer may be disposed between the package cover and the second side of the cold plate, and one or more surfaces of second side of the cold plate may be spaced apart from the package cover to define a coolant channel therebetween. The adhesive layer may seal the package cover to the cold plate around a perimeter of the coolant channel.
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