公开(公告)号：US06441638B2

公开(公告)日：2002-08-27

申请号：US09215456

申请日：1998-12-17

Applicant: Hideki Osaka ,  Shinichi Suzuki ,  Akira Yamagiwa ,  Toshiro Takahashi

Inventor： Hideki Osaka ,  Shinichi Suzuki ,  Akira Yamagiwa ,  Toshiro Takahashi

IPC: H03K1716

CPC classification number: G06F13/4086

Abstract: A bus system with an improved propagation velocity, comprising main lines, and a plurality of stub lines provided on a one-to-one correspondence with a plurality of modules, and connecting the corresponding modules to the main lines.

Abstract translation: 具有改善的传播速度的总线系统，包括主线，以及与多个模块一一对应地提供的多个短截线，并将相应的模块连接到主线。

公开(公告)号：US06438012B1

公开(公告)日：2002-08-20

申请号：US09569876

申请日：2000-05-12

Applicant: Hideki Osaka ,  Toyohiko Komatsu ,  Takashi Tsunehiro ,  Koichi Kimura ,  Susumu Hatano ,  Kazuya Ito ,  Toshio Sugano

Inventor： Hideki Osaka ,  Toyohiko Komatsu ,  Takashi Tsunehiro ,  Koichi Kimura ,  Susumu Hatano ,  Kazuya Ito ,  Toshio Sugano

IPC: G11C800

CPC classification number: G11C5/063 ,  G11C5/04

Abstract: Conventionally, wiring length occupied by a directional coupler decides intervals between modules connected to a bus, and those intervals can not be shortened furthermore. Accordingly, the intervals between modules are wide and high-density mounting is not possible. In the present invention, a directional coupler in a memory bus is formed by a leader line from a controller and a leader line from a memory chip and contained within a memory module. Accordingly, pitch between the modules can be reduced and high-density mounting can be realized.

Abstract translation: 常规地，由定向耦合器占用的布线长度决定了连接到总线的模块之间的间隔，并且这些间隔不能进一步缩短。 因此，模块之间的间隔宽，并且高密度安装是不可能的。 在本发明中，存储器总线中的定向耦合器由来自控制器的引线和来自存储器芯片的引出线形成并且包含在存储器模块中。 因此，可以减少模块之间的间距并实现高密度的安装。

公开(公告)号：US08680881B2

公开(公告)日：2014-03-25

申请号：US13044717

申请日：2011-03-10

Applicant: Yutaka Uematsu ,  Hideki Osaka ,  Satoshi Nakamura ,  Satoshi Muraoka ,  Mitsuaki Katagiri ,  Ken Iwakura ,  Yukitoshi Hirose

Inventor： Yutaka Uematsu ,  Hideki Osaka ,  Satoshi Nakamura ,  Satoshi Muraoka ,  Mitsuaki Katagiri ,  Ken Iwakura ,  Yukitoshi Hirose

IPC: G01R31/00

CPC classification number: G01R31/2889

Abstract: An interposer to be mounted with an integrated circuit to be a test object is provided with a switch and a probe to detect an electric current corresponding to individual terminals of the integrated circuit. A test pattern signal is then inputted to the integrated circuit through a test substrate as a switch that is connected to a power supply terminal of the integrated circuit and that is turned off. If the integrated circuit normally operates and the current values of all the terminals of the integrated circuit are within a tolerance, the power supply terminal connected to the turned-off switch is identified as a terminal that may be removed.

Abstract translation: 安装有作为测试对象的集成电路的插入器设置有用于检测与集成电路的各个端子相对应的电流的开关和探头。 然后，通过作为与集成电路的电源端子连接并断开的开关的测试基板将测试图形信号输入到集成电路。 如果集成电路正常工作，并且集成电路的所有端子的电流值都在容差内，则连接到关断开关的电源端子被识别为可以被去除的端子。

公开(公告)号：US08355258B2

公开(公告)日：2013-01-15

申请号：US13155204

申请日：2011-06-07

Applicant: Hideki Osaka ,  Yutaka Uematsu

Inventor： Hideki Osaka ,  Yutaka Uematsu

IPC: H05K1/00

CPC classification number: H05K3/0005 ,  H05K1/0231 ,  H05K2201/093

Abstract: An orthogonal array is formed by performing electromagnetic field analysis only once and determining a range by using the mount position and type of a capacitor and the number of capacitors as parameters to perform circuit analysis a small number of times. An estimation equation is formed by using as an index a result of the absolute value of the calculated power source impedance, and a capacitor is disposed to reduce noises by using the estimation equation.

Abstract translation: 仅通过执行电磁场分析一次形成正交阵列，并且通过使用电容器的安装位置和类型以及电容器数量作为参数来确定范围以进行电路分析次数少。 通过使用计算的电源阻抗的绝对值的结果作为指标来形成估计方程，并且通过使用估计方程来设置电容器以减少噪声。

公开(公告)号：US07986037B2

公开(公告)日：2011-07-26

申请号：US12068606

申请日：2008-02-08

Applicant: Yutaka Uematsu ,  Tatsuya Saito ,  Hideki Osaka ,  Yoji Nishio ,  Shunichi Saito

Inventor： Yutaka Uematsu ,  Tatsuya Saito ,  Hideki Osaka ,  Yoji Nishio ,  Shunichi Saito

IPC: H01L23/52

CPC classification number: H05K1/0231 ,  H01L23/50 ,  H01L23/5385 ,  H01L23/66 ,  H01L2224/16225 ,  H01L2924/12044 ,  H01L2924/3011 ,  H05K1/09 ,  H05K1/111 ,  H05K1/167 ,  H05K2201/0352 ,  H05K2201/0391 ,  H05K2201/09236 ,  H05K2201/09309 ,  H05K2201/09481 ,  H05K2201/09781 ,  H05K2201/10636 ,  H05K2201/10674 ,  Y02P70/611 ,  H01L2924/00

Abstract: As a power feed route in a semiconductor chip, a power feed route which reduces antiresonance impedance in the frequency range of tens of MHz is to be realized thereby to suppress power noise in a semiconductor device. By inserting structures which raise the resistance in the medium frequency band into parts where the resistance is intrinsically high, such as power wiring in a semiconductor package and capacitor interconnecting electrode parts, the antiresonance impedance in the medium frequency band can be effectively reduced while keeping the impedance low at the low frequency.

Abstract translation: 作为半导体芯片中的馈电路径，可以实现降低数十MHz频率范围内的反谐振阻抗的馈电路径，从而抑制半导体器件的功率噪声。 通过插入将中频带中的电阻提升到电阻本身较高的部分的结构，例如半导体封装中的功率布线和电容器互连电极部件，可以有效地减少中频带中的反谐振阻抗，同时保持 阻抗低在低频。

公开(公告)号：US07957150B2

公开(公告)日：2011-06-07

申请号：US12361761

申请日：2009-01-29

Applicant: Hideki Osaka ,  Yutaka Uematsu

Inventor： Hideki Osaka ,  Yutaka Uematsu

IPC: H05K1/00

CPC classification number: H05K3/0005 ,  H05K1/0231 ,  H05K2201/093

Abstract: An orthogonal array is formed by performing electromagnetic field analysis only once and determining a range by using the mount position and type of a capacitor and the number of capacitors as parameters to perform circuit analysis a small number of times. An estimation equation is formed by using as an index a result of the absolute value of the calculated power source impedance, and a capacitor is disposed to reduce noises by using the estimation equation.

Abstract translation: 仅通过执行电磁场分析一次形成正交阵列，并且通过使用电容器的安装位置和类型以及电容器数量作为参数来确定范围以进行电路分析次数少。 通过使用计算的电源阻抗的绝对值的结果作为指标来形成估计方程，并且通过使用估计方程来设置电容器以减少噪声。

公开(公告)号：US07760531B2

公开(公告)日：2010-07-20

申请号：US11511262

申请日：2006-08-29

Applicant: Yoji Nishio ,  Seiji Funaba ,  Yutaka Uematsu ,  Hideki Osaka

Inventor： Yoji Nishio ,  Seiji Funaba ,  Yutaka Uematsu ,  Hideki Osaka

IPC: G11C5/02

CPC classification number: G11C5/147 ,  G11C5/02 ,  G11C7/02 ,  H01L24/48 ,  H01L2224/05554 ,  H01L2224/4809 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/4847 ,  H01L2924/00014 ,  H01L2924/10161 ,  H01L2924/15183 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2224/45099 ,  H01L2224/05599 ,  H01L2924/00012

Abstract: A semiconductor module includes a first semiconductor device, a second semiconductor device and a reference voltage supplying circuit. The first semiconductor device includes a first electrode. The second semiconductor device includes a second electrode. The reference voltage supplying circuit is for supplying a reference potential to the first electrode and the second electrode and for suppressing a noise to be transferred between the first electrode and the second electrode.

Abstract translation: 半导体模块包括第一半导体器件，第二半导体器件和参考电压提供电路。 第一半导体器件包括第一电极。 第二半导体器件包括第二电极。 参考电压提供电路用于向第一电极和第二电极提供参考电位，并用于抑制在第一电极和第二电极之间传递的噪声。

公开(公告)号：US20090213558A1

公开(公告)日：2009-08-27

申请号：US12361761

申请日：2009-01-29

Applicant: Hideki OSAKA ,  Yutaka Uematsu

Inventor： Hideki OSAKA ,  Yutaka Uematsu

IPC: H05K1/18

CPC classification number: H05K3/0005 ,  H05K1/0231 ,  H05K2201/093

Abstract: An orthogonal array is formed by performing electromagnetic field analysis only once and determining a range by using the mount position and type of a capacitor and the number of capacitors as parameters to perform circuit analysis a small number of times. An estimation equation is formed by using as an index a result of the absolute value of the calculated power source impedance, and a capacitor is disposed to reduce noises by using the estimation equation.

Abstract translation: 仅通过执行电磁场分析一次形成正交阵列，并且通过使用电容器的安装位置和类型以及电容器数量作为参数来确定范围以进行电路分析次数少。 通过使用计算的电源阻抗的绝对值的结果作为指标来形成估计方程，并且通过使用估计方程来设置电容器以减少噪声。

公开(公告)号：US07475179B2

公开(公告)日：2009-01-06

申请号：US10517591

申请日：2003-07-01

Applicant: Hideki Osaka

Inventor： Hideki Osaka

IPC: G06F13/00 ,  G06F13/14 ,  H01P5/04 ,  H01P5/12 ,  H01P5/18 ,  H03H2/00

CPC classification number: G06F13/4086

Abstract: In ultrahigh speed data transfer, a drive pulse is attenuated due to a skin effect and a dielectric loss, and a tail generated by a sub coupler extends as the drive pulse propagates on the main line. For that reason, an intersymbol interference becomes large, which causes jitters. In a memory system to which a plurality of DRAM memory modules are connected, in order to transfer data at high-speed, directional couplers are wired between a main controller and each of the modules, and the coupling lengths become longer with farther ends, thereby suppressing jitters. The directional couplers are wired between the main controller and each of the modules, and the coupling lengths are made longer with the farther ends with the results that the generated signal amounts are made constant, and jitters of the wiring and receiver delay are suppressed.

Abstract translation: 在超高速数据传输中，驱动脉冲由于皮肤效应和介电损耗而衰减，并且由辅助耦合器产生的尾部随着驱动脉冲在主线上传播而延长。 因此，码间干扰变大，导致抖动。 在连接有多个DRAM存储器模块的存储器系统中，为了在高速下传输数据，定向耦合器布线在主控制器和每个模块之间，并且耦合长度随着更远的端部变长，从而 抑制不安 定向耦合器连接在主控制器和每个模块之间，并且耦合长度随着更远的端部变长而产生的信号量变得恒定，并且抑制了布线和接收器延迟的抖动。

公开(公告)号：US20080258259A1

公开(公告)日：2008-10-23

申请号：US12107758

申请日：2008-04-22

Applicant: Hideki OSAKA ,  Tatsuya Saito

Inventor： Hideki OSAKA ,  Tatsuya Saito

IPC: H01L45/00

CPC classification number: H01L25/0657 ,  H01L23/481 ,  H01L23/50 ,  H01L23/642 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L2224/0554 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/48091 ,  H01L2224/48145 ,  H01L2224/48227 ,  H01L2224/49171 ,  H01L2224/73257 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06572 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01023 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01077 ,  H01L2924/014 ,  H01L2924/12041 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/19104 ,  H01L2924/19105 ,  H01L2924/19107 ,  H01L2924/30105 ,  H01L2924/30107 ,  H01L2924/3011 ,  H01L2924/3025 ,  Y10S257/904 ,  Y10S257/924 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/05599 ,  H01L2924/00012 ,  H01L2224/0555 ,  H01L2224/0556

Abstract: A semiconductor chip and a semiconductor device mounting the semiconductor chip capable of increasing a capacitance of a capacitor without reducing the number of signal bumps or power bumps of a package and the number of C4 solder balls of the semiconductor chip, and achieving a stable power supply with suppressing fluctuations of power at a resonance frequency without a limitation in a position to mount a capacitor for lowering noise of a signal transceiving interface block. In the semiconductor device, a via hole is provided to the semiconductor chip, a power-supply electrode connected to the via hole is provided to a back surface of the semiconductor chip, and a capacitor is mounted to the electrode on the back surface. And, a high-resistance material is used for a material of a power-supply via hole inside the semiconductor chip, thereby increasing the resistance and lowering the Q factor.

Abstract translation: 一种半导体芯片和半导体器件，其安装半导体芯片能够增加电容器的电容而不减少封装的信号凸块或功率凸块的数量以及半导体芯片的C 4焊球的数量，并且实现稳定的功率 在谐振频率下抑制功率波动而不受限于安装用于降低信号收发接口块噪声的电容器的位置。 在半导体装置中，在半导体芯片上设置有通孔，在该半导体芯片的背面设有与通路孔连接的电源电极，在背面的电极上安装有电容器。 并且，高电阻材料用于半导体芯片内的电源通孔的材料，从而增加电阻并降低Q因子。