公开(公告)号：US07816219B2

公开(公告)日：2010-10-19

申请号：US11850076

申请日：2007-09-05

Applicant: Xiangdong Chen ,  Sunfei Fang ,  Zhijiong Luo ,  Haining Yang ,  Huilong Zhu

Inventor： Xiangdong Chen ,  Sunfei Fang ,  Zhijiong Luo ,  Haining Yang ,  Huilong Zhu

IPC: H01L21/336

CPC classification number: H01L29/7833 ,  H01L29/665 ,  H01L29/6659

Abstract: A semiconductor structure and method for forming the same. First, a semiconductor structure is provided, including (a) a semiconductor layer including (i) a channel region and (ii) first and second source/drain (S/D) extension regions, and (iii) first and second S/D regions, (b) a gate dielectric region in direction physical contact with the channel region via a first interfacing surface that defines a reference direction essentially perpendicular to the first interfacing surface, and (c) a gate region in direct physical contact with the gate dielectric region, wherein the gate dielectric region is sandwiched between and electrically insulates the gate region and the channel region. Then, (i) a first shallow contact region is formed in direct physical contact with the first S/D extension region, and (ii) a first deep contact region is formed in direct physical contact with the first S/D region and the first shallow contact region.

Abstract translation: 一种半导体结构及其形成方法。 首先，提供半导体结构，其包括（a）包括（i）沟道区和（ii）第一和第二源/漏（S / D）延伸区的半导体层，以及（iii）第一和第二S / D 区域，（b）通过限定基本上垂直于第一接口表面的参考方向的第一接口表面方向与沟道区域物理接触的栅极电介质区域，以及（c）与栅极电介质直接物理接触的栅极区域 区域，其中栅极电介质区域夹在栅极区域和沟道区域之间并使电绝缘。 然后，（i）第一浅接触区域形成为与第一S / D延伸区域直接物理接触，并且（ii）第一深接触区域形成为与第一S / D区域和第一浅/ 浅接触区域。

公开(公告)号：US07790540B2

公开(公告)日：2010-09-07

申请号：US11467186

申请日：2006-08-25

Applicant: Haining Yang ,  Wai-Kin Li

Inventor： Haining Yang ,  Wai-Kin Li

IPC: H01L21/8238

CPC classification number: H01L21/823807 ,  H01L21/823864 ,  H01L27/092 ,  H01L29/7843

Abstract: A low k stress liner, which replaces conventional stress liners in CMOS devices, is provided. In one embodiment, a compressive, low k stress liner is provided which can improve the hole mobility in pFET devices. UV exposure of this compressive, low k material results in changing the polarity of the low k stress liner from compressive to tensile. The use of such a tensile, low k stress liner improves electron mobility in nFET devices.

Abstract translation: 提供了一种代替CMOS器件中常规应力衬垫的低k应力衬垫。 在一个实施例中，提供压缩的低k应力衬垫，其可以改善pFET器件中的空穴迁移率。 这种压缩低k材料的紫外线暴露导致低k应力衬垫的极性从压缩变为拉伸。 使用这种拉伸的低k应力衬垫提高nFET器件中的电子迁移率。

公开(公告)号：US07737014B2

公开(公告)日：2010-06-15

申请号：US10596249

申请日：2003-12-08

Applicant: Frederick William Buehrer ,  Dureseti Chidambarrao ,  Bruce B. Doris ,  Hsiang-Jen Huang ,  Haining Yang

Inventor： Frederick William Buehrer ,  Dureseti Chidambarrao ,  Bruce B. Doris ,  Hsiang-Jen Huang ,  Haining Yang

IPC: H01L21/22 ,  H01L21/38

CPC classification number: H01L29/7842 ,  H01L21/22 ,  H01L21/26513 ,  H01L21/26586 ,  H01L21/324 ,  H01L21/823807 ,  H01L21/823814 ,  H01L29/1083 ,  H01L29/6653 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/7843

Abstract: A stressed film applied across a boundary defined by a structure or a body (e.g. substrate or layer) of semiconductor material provides a change from tensile to compressive stress in the semiconductor material proximate to the boundary and is used to modify boron diffusion rate during annealing and thus modify final boron concentrations. In the case of a field effect transistor, the gate structure may be formed with or without sidewalls to regulate the location of the boundary relative to source/drain, extension and/or halo implants. Different boron diffusion rates can be produced in the lateral and vertical directions and diffusion rates comparable to arsenic can be achieved. Reduction of junction capacitance of both nFETs and pFETs can be achieved simultaneously with the same process steps.

Abstract translation: 应用于由半导体材料的结构或主体（例如衬底或层）限定的边界处的应力膜提供了靠近边界的半导体材料中的拉应力和压缩应力的变化，并用于在退火过程中修饰硼扩散速率， 从而改变最终的硼浓度。 在场效应晶体管的情况下，栅极结构可以形成有或不具有侧壁以调节边界相对于源极/漏极，延伸和/或晕轮植入物的位置。 可以在横向和垂直方向上产生不同的硼扩散速率，并且可以实现与砷相当的扩散速率。 可以通过相同的工艺步骤同时实现nFET和pFET的结电容的减小。

公开(公告)号：US07732270B2

公开(公告)日：2010-06-08

申请号：US11972964

申请日：2008-01-11

Applicant: Dureseti Chidambarrao ,  Ying Li ,  Rajeev Malik ,  Shreesh Narasimha ,  Haining Yang ,  Huilong Zhu

Inventor： Dureseti Chidambarrao ,  Ying Li ,  Rajeev Malik ,  Shreesh Narasimha ,  Haining Yang ,  Huilong Zhu

IPC: H01L21/8238

CPC classification number: H01L29/7843 ,  H01L21/823807 ,  H01L29/66772 ,  Y10S438/938

Abstract: The present invention provides a semiconductor device having dual nitride liners, which provide an increased transverse stress state for at least one FET and methods for the manufacture of such a device. A first aspect of the invention provides a method for use in the manufacture of a semiconductor device comprising the steps of applying a first silicon nitride liner to the device and applying a second silicon nitride liner adjacent the first silicon nitride liner, wherein at least one of the first and second silicon nitride liners induces a transverse stress in a silicon channel beneath at least one of the first and second silicon nitride liner.

Abstract translation: 本发明提供一种具有双重氮化物衬垫的半导体器件，其为至少一个FET提供增加的横向应力状态以及用于制造这种器件的方法。 本发明的第一方面提供了一种用于制造半导体器件的方法，包括以下步骤：将第一氮化硅衬垫施加到器件上并施加与第一氮化硅衬垫相邻的第二氮化硅衬垫，其中至少一个 第一和第二氮化硅衬垫在第一和第二氮化硅衬里中的至少一个之下的硅沟道中引起横向应力。

公开(公告)号：US07678658B2

公开(公告)日：2010-03-16

申请号：US12018440

申请日：2008-01-23

Applicant: Haining Yang ,  Robert C. Wong

Inventor： Haining Yang ,  Robert C. Wong

IPC: H01L21/20

CPC classification number: H01L27/1104 ,  H01L21/84 ,  H01L27/0207 ,  H01L27/11 ,  H01L27/1203

Abstract: A method of forming an improved static random access memory (SRAM) interconnect structure is provided. The method includes forming a sidewall spacer around a periphery of a patterned poly-silicon layer formed over a silicon layer of a semiconductor substrate; removing the patterned poly-silicon layer for exposing a portion of a cap layer; etching the exposed portion of the cap layer for revealing a portion of the silicon layer; etching the portion of the silicon layer, in which a portion of said silicon layer connects at least a portion of pull-down device of said SRAM to at least a portion of pull-up device of said SRAM; forming a gate oxide; and forming a gate conductor over the gate oxide. An interconnect structure is also provided.

Abstract translation: 提供了形成改进的静态随机存取存储器（SRAM）互连结构的方法。 该方法包括在形成在半导体衬底的硅层上的图案化多晶硅层的周围形成侧壁隔离物; 去除图案化的多晶硅层以暴露盖层的一部分; 蚀刻盖层的暴露部分以露出硅层的一部分; 蚀刻硅层的部分，其中所述硅层的一部分将所述SRAM的下拉器件的至少一部分连接到所述SRAM的上拉器件的至少一部分; 形成栅极氧化物; 以及在所述栅极氧化物上形成栅极导体。 还提供互连结构。

公开(公告)号：US07553760B2

公开(公告)日：2009-06-30

申请号：US11550966

申请日：2006-10-19

Applicant: Haining Yang ,  Wai-Kin Li

Inventor： Haining Yang ,  Wai-Kin Li

IPC: H01L21/302

CPC classification number: H01L23/5329 ,  B81C1/00095 ,  B81C2201/0149 ,  B81C2201/0198 ,  B82Y30/00 ,  H01L21/0337 ,  H01L21/0338 ,  H01L21/31144 ,  H01L21/76808 ,  H01L21/76811 ,  H01L21/76813 ,  H01L21/76816 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method to form interconnect structures including nano-scale, e.g., sub-lithographic, lines and vias for future generation of semiconductor technology using self-assembly block copolymers that can be placed at a specific location using a pre-fabricated hard mask pattern is provided. The inventive method provides an interconnect structure in which the line is self-aligned to the via.

Abstract translation: 提供了一种形成互连结构的方法，包括纳米尺度，例如亚光刻，线和通孔，用于使用可以使用预制的硬掩模图案放置在特定位置的自组装嵌段共聚物的半导体技术的未来生成 。 本发明的方法提供了一种互连结构，其中线路与通孔自对准。

公开(公告)号：US07550351B2

公开(公告)日：2009-06-23

申请号：US11538850

申请日：2006-10-05

Applicant: Haining Yang ,  Xiangdong Chen

Inventor： Haining Yang ,  Xiangdong Chen

IPC: H01L21/336 ,  H01L21/8234 ,  H01L21/8238 ,  H01L21/331

CPC classification number: H01L21/823835 ,  H01L21/823842 ,  H01L27/092

Abstract: The invention is directed to an improved transistor that reduces dopant cross-diffusion and improves chip density. A first embodiment of the invention comprises gate electrode material partially removed at a junction of a first gate electrode region comprised of gate material doped with first ions for a first device and second gate electrode region comprised of gate material doped with second ions for a second device. The respectively doped regions are connected by a silicide layer near the top surface of the gate conductors.

Abstract translation: 本发明涉及减少掺杂剂交叉扩散并改善芯片密度的改进的晶体管。 本发明的第一实施例包括在由掺杂有用于第一器件的第一离子的栅极材料构成的第一栅极电极区域和由掺杂有第二离子的栅极材料构成的第二栅极电极区域的第一栅极电极区域处部分去除的栅电极材料，用于第二器件 。 分别掺杂的区域通过靠近栅极导体的顶表面的硅化物层连接。

公开(公告)号：US07544608B2

公开(公告)日：2009-06-09

申请号：US11458464

申请日：2006-07-19

Applicant: Chih-Chao Yang ,  Keith Kwong Hon Wong ,  Haining Yang

Inventor： Chih-Chao Yang ,  Keith Kwong Hon Wong ,  Haining Yang

IPC: H01L21/00

CPC classification number: H01L23/53295 ,  H01L21/7682 ,  H01L21/76835 ,  H01L23/5222 ,  H01L23/53238 ,  H01L23/5329 ,  H01L2221/1047 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method for manufacturing a structure includes depositing a dense dielectric over the entire wafer, which includes areas that require low dielectric capacitance and areas that require high mechanical strength. The method further includes masking areas of the dense dielectric over the areas that require high mechanical strength and curing unmasked areas of the dense dielectric to burn out porogens inside the dense dielectric and transform the unmasked areas of the dense dielectric to porous dielectric material. A semiconductor structure comprises porous and dense hybrid interconnects for high performance and reliability semiconductor applications.

Abstract translation: 一种用于制造结构的方法包括在整个晶片上沉积致密电介质，其包括需要低介电电容的区域和需要高机械强度的区域。 该方法还包括在需要高机械强度的区域和致密电介质的固化未掩蔽区域的区域上掩蔽致密电介质的区域，以烧尽致密电介质内的致孔剂，并将致密电介质的未掩模区域转化为多孔电介质材料。 半导体结构包括用于高性能和可靠性半导体应用的多孔和致密的混合互连。

公开(公告)号：US07514339B2

公开(公告)日：2009-04-07

申请号：US11621124

申请日：2007-01-09

Applicant: Haining Yang ,  Wai-Kin Li

Inventor： Haining Yang ,  Wai-Kin Li

IPC: H01L21/30

CPC classification number: H01L21/76283 ,  H01L21/3086

Abstract: A method of isolating semiconductor devices formed on a semiconductor substrate having a silicon on insulator (SOI) layer is provided. The method includes forming at least one shallow trench area on a pad nitride layer deposited on a surface of the SOI layer, wherein the at least one shallow trench area includes an opening for exposing a portion of the SOI layer; applying diblock copolymer material over the pad nitride layer and the at least one shallow trench area; annealing the applied copolymer material to form self-organized patterns; and partially etching the shallow trench area using the diblock copolymer material as an etch mask. A semiconductor structures is also described having an isolation structure formed on a SOI layer of a semiconductor substrate the isolation structure having an oxidized substrate region; and a void region formed on the oxidized substrate region.

Abstract translation: 提供了一种隔离形成在具有绝缘体上硅（SOI）层的半导体衬底上的半导体器件的方法。 该方法包括在沉积在SOI层的表面上的衬垫氮化物层上形成至少一个浅沟槽区，其中至少一个浅沟槽区包括用于暴露SOI层的一部分的开口; 在所述衬垫氮化物层和所述至少一个浅沟槽区域上施加二嵌段共聚物材料; 退火所应用的共聚物材料以形成自组织图案; 并使用二嵌段共聚物材料作为蚀刻掩模部分蚀刻浅沟槽区域。 还描述了半导体结构，其具有形成在半导体衬底的SOI层上的隔离结构，该隔离结构具有氧化的衬底区域; 以及形成在氧化的基板区域上的空隙区域。

公开(公告)号：US20080293257A1

公开(公告)日：2008-11-27

申请号：US12186923

申请日：2008-08-06

Applicant: Chih-Chao Yang ,  Haining Yang ,  Keith Kwong Hon Wong

Inventor： Chih-Chao Yang ,  Haining Yang ,  Keith Kwong Hon Wong

IPC: H01L21/768

CPC classification number: H01L21/76829 ,  H01L21/76834 ,  Y10S438/927

Abstract: A high tensile stress capping layer on Cu interconnects in order to reduce Cu transport and atomic voiding at the Cu/dielectric interface. The high tensile dielectric film is formed by depositing multiple layers of a thin dielectric material, each layer being under approximately 50 angstroms in thickness. Each dielectric layer is plasma treated prior to depositing each succeeding dielectric layer such that the dielectric cap has an internal tensile stress.

Abstract translation: Cu互连上的高拉伸应力覆盖层，以减少Cu /介电界面处的铜迁移和原子排空。 高拉伸电介质膜通过沉积多层薄的电介质材料形成，每个层的厚度在约50埃以下。 每个电介质层在沉积每个后续介电层之前进行等离子体处理，使得电介质盖具有内部拉伸应力。