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公开(公告)号：US11759177B2
公开(公告)日：2023-09-19
申请号：US17287531
申请日：2020-05-15
Inventor： Ming Yuchi , Mingyue Ding , Zhaohui Liu , Qiude Zhang , Junjie Song , Shanshan Wang , Liang Zhou , Kuolin Liu
CPC classification number: A61B8/483 , A61B8/085 , A61B8/0825 , A61B8/145 , A61B8/4411 , A61B8/5215 , G01S15/8927 , G01S15/8993
Abstract: A three-dimensional ultrasound tomography method and system based on spiral scanning are provided. The method includes the following. (1) Collecting raw data: an emission array element is switched while a probe maintains a uniform linear motion, so that changes in trajectory with time of a position of an equivalent emission array element in a three-dimensional space show a spiral or a partial spiral, and echo data is received. (2) Pre-processing data. (3) Calculating coordinates of each equivalent emission array element. (4) Calculating coordinates of an imaging focus point. (5) Performing synthetic aperture focusing on each imaging focus point. (6) Post-processing data. The disclosure improves the principle of the imaging method, the design of the overall process, etc. Volume data containing information of continuous tissue layers is obtained through spiral scanning. Applying the synthetic aperture focusing technique in the three-dimensional space improves the resolution between layers and shorten the scan time.
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42.发明授权公开(公告)号：US11722965B2
公开(公告)日：2023-08-08
申请号：US18058994
申请日：2022-11-28
CPC classification number: H04W52/029 , G06F17/18
Abstract: A method for optimizing a mobile phone terminal based on a probability of an energy consumption-related interruption is disclosed. The method includes: S1. predicting a probability of an energy consumption-related interruption in real time; and S2. adjusting an operating frequency of a baseband chip of a mobile phone terminal according to the predicted probability of an energy consumption-related interruption.
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公开(公告)号：US11714836B2
公开(公告)日：2023-08-01
申请号：US17455502
申请日：2021-11-18
Inventor： Jiang Xiao , Jian Chang , Rui Han , Xiaohai Dai , Hai Jin
IPC: G06F16/2457 , G06F16/248 , G06F16/28 , G06Q20/38
CPC classification number: G06F16/288 , G06F16/248 , G06F16/24575 , G06F16/285 , G06Q20/3823 , G06Q20/3827
Abstract: The present invention relates a method for high-performance traceability query oriented to multi-chain data association, comprising: identifying a target transaction needing the traceability query; searching out all corresponding target chains based on cross-chain transaction data association; making query requests parallelly; and executing the query among the target chains according to a key value of the target transaction and returning query results. The blockchain traceability query method proposed by the present invention is different from serialized block data query conducted in the chain-type structure, and the disclosed cross-chain query operation can be parallelly executed, leading to improved efficiency of traceability query. Opposite to the conventional blockchain where blocks are used as nodes of chains, the present invention directly uses sub blockchains as nodes of the SRB. Since sub blockchains can be dynamically added or removed, the present invention enhances the scalability of the entire system.
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公开(公告)号：US20230170908A1
公开(公告)日：2023-06-01
申请号：US17794620
申请日：2021-07-05
Inventor： Xingsheng WANG , Yujie SONG , Qiwen WU , Xiangshui MIAO
IPC: H03K19/1776 , G11C13/00
CPC classification number: H03K19/1776 , G11C13/004 , G11C13/0069 , H03K19/21
Abstract: A non-volatile Boolean logic circuit based on memristors and an operation method, which performs logic operations on the input logic value P and/or the input logic value Q. The logic circuit includes: a controller, a memristor M1, a memristor M2 and a resistor. The controller sets the memristor M2 to a high resistance state before performing the logic operation. When performing the logic operation, a voltage A is applied to the memristor M1, a voltage B is applied to the memristor M2, a voltage C is applied to the resistor. The resistance state of the memristor M2 is the result of the logic operation. When a logic operation is performed on the logic value P and the logic value Q or only on the logic value Q, the controller further sets the memristor M1 to the resistance state corresponding to the logic value Q before performing the logic operation.
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公开(公告)号：US20230150114A1
公开(公告)日：2023-05-18
申请号：US17864338
申请日：2022-07-13
Inventor： Cai-Hua Xiong , Tao WANG , Di Hu , jie jun yi Liang , Yuhao Li , Tian-Cheng Zhou , Wen-Bin Chen
CPC classification number: B25J9/0006 , A61H1/0266 , A61H2201/1642 , A61H2003/007
Abstract: A passive exoskeleton based on energy flow characteristics of a foot-ankle complex includes a first passive exoskeleton. The first passive exoskeleton includes an energy distribution mechanism, a strike-recipient mechanism and a wearing fixing assembly. The energy distribution mechanism is connected to the strike-recipient mechanism, and the energy distribution mechanism is also connected to the wearing fixing assembly. The energy distribution mechanism includes a ratchet wheel shaft, a left torsional spring, a right torsional spring and a middle guide wheel respectively sleeved on the ratchet wheel shaft. The middle guide wheel is connected to the wearing fixing assembly through an ankle joint power-assisted cord. The ratchet wheel shaft is connected to the strike-recipient mechanism, the strike-recipient mechanism drives the ratchet wheel shaft to rotate, and the ratchet wheel shaft drives the left torsional spring, the right torsional spring and the middle guide wheel to rotate.
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Patent Agency Ranking
公开(公告)号：US11609787B2
公开(公告)日：2023-03-21
申请号：US16947055
申请日：2020-07-16
Inventor： Xiaofei Liao , Yicheng Chen , Yu Zhang , Hai Jin , Jin Zhao , Xiang Zhao , Beibei Si
Abstract: The present disclosure relates to an FPGA-based dynamic graph processing method, comprising: where graph mirrors of a dynamic graph that have successive timestamps define an increment therebetween, a pre-processing module dividing the graph mirror having the latter timestamp into at least one path unit in a manner that incremental computing for any vertex only depends on a preorder vertex of that vertex; an FPGA processing module storing at least two said path units into an on-chip memory directly linked to threads in a manner that every thread unit is able to process the path unit independently; the thread unit determining an increment value between the successive timestamps of the preorder vertex while updating a state value of the preorder vertex, and transferring the increment value to a succeeding vertex adjacent to the preorder vertex in a transfer direction determined by the path unit, so as to update the state value of the succeeding vertex.
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47.发明授权公开(公告)号：US11609443B2
公开(公告)日：2023-03-21
申请号：US16764403
申请日：2018-06-07
Inventor： Xiangshui Miao , Yitao Lu , Hao Tong , Yi Wang
Abstract: Disclosed in the present invention are a chalcogenide phase change material based all-optical switch and a manufacturing method therefor, relating to the field of optical communications. The all-optical switch comprises: stacked in sequence, a cover layer film, a chalcogenide phase change material film, an isolation layer film, a silicon photonic crystal, and a substrate. The silicon photonic crystal comprises a nano-porous structure such that the silicon photonic crystal has a Fano resonance effect. When the all-optical switch is used, the state of the chalcogenide phase change material film is controlled by means of laser, and the resonance state of the silicon photonic crystal is modulated to implement modulation of signal light transmissivity; the modulation range is within a communication band from 1500 nm to 1600 nm, thereby implementing an optical switch. The all-optical switch of the present invention has the characteristics of high contrast ratio, high rate and low loss.
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公开(公告)号：US20230072565A1
公开(公告)日：2023-03-09
申请号：US17823620
申请日：2022-08-31
Inventor： Hai'ou Zhang , Kai Wang , Fusheng Dai , Xushan Zhao , Runsheng Li , Jun Wu , Haitao Yang , Huayu Zhang
Abstract: Wire arc additive manufacturing-spinning combined machining device and method are provided. The machining device includes a spinning mechanism and a fused deposition modeling mechanism. The spinning mechanism includes a machine tool and a spinning head. The spinning head is installed on the machine tool by a main shaft, and the main shaft is configured to drive the spinning head to rotate to achieve the movement in three vertical directions. The spinning head includes a spinning base and balls. Each of the balls is installed in a corresponding one of arc grooves at a bottom of the spinning base. The fused deposition modeling mechanism includes a moving track, a robot and a heat source generator. The arc moving track is arranged around the machine tool in a surrounding mode. The robot is movably installed on the moving track. The heat source generator is installed at a tail end of the robot.
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公开(公告)号：US11590613B1
公开(公告)日：2023-02-28
申请号：US17690942
申请日：2022-03-09
Inventor： Shengming Yin , Guoqiang Yi , Youwei Yan , Yaju Zhou , Haicheng Tian
IPC: B23K35/30 , C22C35/00 , B23K35/362 , B23K9/04 , B33Y70/00 , B23K103/04 , B33Y80/00
Abstract: The present disclosure belongs to the field of materials with metal structures, and specifically relates to a preparation method for a nano-oxide dispersion strengthened steel. The method includes mixing a ferrochromium alloy, a ferrotungsten alloy, a ferroalloy containing a rare earth element, an oxygen source and a reduced iron powder to obtain a mixture; wrapping the mixture in a steel strip, and conducting drawing reducing to obtain a flux-cored wire; and conducting arc additive manufacturing on the flux-cored wire on a substrate, and then conducting heat treatment to obtain the nano-oxide particle dispersion strengthened steel.
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50.发明申请公开(公告)号：US20230046115A1
公开(公告)日：2023-02-16
申请号：US17564241
申请日：2021-12-29
Inventor： Haiqing Wei , Shiyuan Liu , Hao Jiang
Abstract: A method and a system for correcting lithography process hotspots based on stress damping adjustment are provided. The method includes: acquiring a mark hotspot of a mask pattern; forming N annuli centered on the mark hotspot from inner to outer on a mask; moving vertexes of the mask pattern located in each annulus by a specific distance in a direction deviating from the mark hotspot and connecting the moved vertexes according to an original connection relationship to acquire an updated layout; verifying electrical characteristics of the updated layout, determining whether a deviation of the electrical characteristics of the updated layout is within a tolerable range, and performing geometric correction to compensate for a deviation of electrical parameters if no is determined and then ending correction, or ending the correction if yes is determined.
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