公开(公告)号：US20180130717A1

公开(公告)日：2018-05-10

申请号：US15865842

申请日：2018-01-09

Applicant: INVENSAS CORPORATION

Inventor： Hong SHEN ,  Charles G. WOYCHIK ,  Arkalgud R. SITARAM

IPC: H01L23/055 ,  H01L23/498 ,  H01L21/48 ,  H01L21/56 ,  H01L21/768 ,  H01L23/04 ,  H01L23/14 ,  H01L23/31 ,  H01L23/367 ,  H01L23/48 ,  H01L21/288 ,  H01L25/00 ,  H01L25/065 ,  H01L23/00 ,  H01L23/538 ,  H01L23/10

CPC classification number: H01L23/055 ,  H01L21/2885 ,  H01L21/4803 ,  H01L21/486 ,  H01L21/56 ,  H01L21/561 ,  H01L21/76879 ,  H01L21/76897 ,  H01L23/04 ,  H01L23/10 ,  H01L23/147 ,  H01L23/3107 ,  H01L23/315 ,  H01L23/3675 ,  H01L23/481 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/49838 ,  H01L23/5389 ,  H01L24/97 ,  H01L25/0652 ,  H01L25/0655 ,  H01L25/50 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2225/06548 ,  H01L2225/06555 ,  H01L2924/12042 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2924/00012

Abstract: Dies (110) with integrated circuits are attached to a wiring substrate (120), possibly an interposer, and are protected by a protective substrate (410) attached to a wiring substrate. The dies are located in cavities in the protective substrate (the dies may protrude out of the cavities). In some embodiments, each cavity surface puts pressure on the die to strengthen the mechanical attachment of the die the wiring substrate, to provide good thermal conductivity between the dies and the ambient (or a heat sink), to counteract the die warpage, and possibly reduce the vertical size. The protective substrate may or may not have its own circuitry connected to the dies or to the wiring substrate. Other features are also provided.

公开(公告)号：US09947643B2

公开(公告)日：2018-04-17

申请号：US15075899

申请日：2016-03-21

Applicant: Invensas Corporation

Inventor： Ilyas Mohammed ,  Masud Beroz ,  Liang Wang

IPC: H01L33/62 ,  H01L25/16 ,  H01L33/06 ,  H01L33/22 ,  H01L33/32 ,  H01L33/60 ,  H01L33/00 ,  H01L33/58

CPC classification number: H01L25/167 ,  H01L33/0079 ,  H01L33/06 ,  H01L33/22 ,  H01L33/32 ,  H01L33/58 ,  H01L33/60 ,  H01L33/62 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Inverted optical device. In accordance with an embodiment of the present invention, a plurality of piggyback substrates are attached to a carrier wafer. The plurality of piggyback substrates are dissimilar in composition to the carrier wafer. The plurality of piggyback substrates are processed, while attached to the carrier wafer, to produce a plurality of integrated circuit devices. A flip wafer is attached to the plurality of light emitting diodes, away from the carrier wafer and the carrier wafer is removed. The plurality of light emitting diodes may be singulated to form individual light emitting diode devices.

公开(公告)号：US09935075B2

公开(公告)日：2018-04-03

申请号：US15237936

申请日：2016-08-16

Applicant: Invensas Corporation

Inventor： Shaowu Huang ,  Javier A. Delacruz

IPC: H01L23/552 ,  H01L23/00 ,  H01L21/56 ,  H01L23/31

CPC classification number: H01L24/49 ,  H01L21/565 ,  H01L23/3114 ,  H01L23/552 ,  H01L24/85 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/49097 ,  H01L2224/49171 ,  H01L2224/49179 ,  H01L2924/15311 ,  H01L2924/19105 ,  H01L2924/19107 ,  H01L2924/3025 ,  H01L2924/00014

Abstract: Apparatuses relating generally to a microelectronic package having protection from electromagnetic interference are disclosed. In an apparatus thereof, a platform has an upper surface and a lower surface opposite the upper surface and has a ground plane. A microelectronic device is coupled to the upper surface of the platform. Wire bond wires are coupled to the ground plane with a pitch. The wire bond wires extend away from the upper surface of the platform with upper ends of the wire bond wires extending above an upper surface of the microelectronic device. The wire bond wires are spaced apart from one another to provide a fence-like perimeter to provide an interference shielding cage. A conductive layer is coupled to at least a subset of the upper ends of the wire bond wires for electrical conductivity to provide a conductive shielding layer to cover the interference shielding cage.

公开(公告)号：US09917042B2

公开(公告)日：2018-03-13

申请号：US15147099

申请日：2016-05-05

Applicant: Invensas Corporation

Inventor： Belgacem Haba ,  Sean Moran

IPC: H01L23/498 ,  H01L21/48 ,  H01L23/00 ,  H01L21/78 ,  H01L25/10 ,  H01L21/56 ,  H01L21/683 ,  H01L23/31 ,  H01L23/367 ,  H01L25/065 ,  H01L25/16 ,  H01L25/18 ,  H01L23/04 ,  H01L25/00

CPC classification number: H01L23/498 ,  H01L21/4846 ,  H01L21/4853 ,  H01L21/486 ,  H01L21/56 ,  H01L21/563 ,  H01L21/6835 ,  H01L21/78 ,  H01L23/04 ,  H01L23/3121 ,  H01L23/3135 ,  H01L23/3142 ,  H01L23/3675 ,  H01L23/49811 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/49838 ,  H01L24/17 ,  H01L24/81 ,  H01L25/0652 ,  H01L25/0655 ,  H01L25/105 ,  H01L25/16 ,  H01L25/18 ,  H01L25/50 ,  H01L2221/68345 ,  H01L2221/68359 ,  H01L2221/68381 ,  H01L2224/16113 ,  H01L2224/16227 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/81192 ,  H01L2224/97 ,  H01L2225/06517 ,  H01L2225/0652 ,  H01L2225/06548 ,  H01L2225/06572 ,  H01L2225/06589 ,  H01L2225/1058 ,  H01L2924/1427 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/19041 ,  H01L2924/19102 ,  H01L2224/81

Abstract: A dielectric element has a plurality of contacts at a first surface and a plurality of first traces coupled thereto which extend in directions parallel to the first surface. A circuit structure made of a plurality of dielectric layers and electrically conductive features thereon includes a plurality of bumps at a first surface which face the contacts of the dielectric element and are joined thereto. Circuit structure contacts at a second surface opposite the first surface are electrically coupled with the bumps through second traces on the circuit structure, the circuit structure contacts configured for connection with a plurality of element contacts of each of a plurality of microelectronic elements, wherein the microelectronic elements can be assembled therewith such that element contacts thereof face and are joined with the circuit structure contacts.

公开(公告)号：US09893033B2

公开(公告)日：2018-02-13

申请号：US15096588

申请日：2016-04-12

Applicant: Invensas Corporation

Inventor： Belgacem Haba ,  Reynaldo Co ,  Rizza Lee Saga Cizek ,  Wael Zohni

IPC: B23K31/02 ,  H01L23/00 ,  B23K20/00 ,  H01L23/498 ,  H01L21/48 ,  H01L21/56

CPC classification number: H01L24/85 ,  B23K20/004 ,  B23K20/005 ,  B23K20/007 ,  H01L21/4853 ,  H01L21/56 ,  H01L23/49811 ,  H01L24/43 ,  H01L24/78 ,  H01L2224/04105 ,  H01L2224/056 ,  H01L2224/432 ,  H01L2224/4382 ,  H01L2224/43985 ,  H01L2224/783 ,  H01L2224/78301 ,  H01L2224/7855 ,  H01L2224/78621 ,  H01L2224/78822 ,  H01L2224/85 ,  H01L2224/85345 ,  H01L2224/85399 ,  H01L2224/96 ,  H01L2924/00014 ,  H01L2924/181 ,  H01L2924/19107 ,  H01L2924/2064 ,  H01L2924/00012 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2224/45099

Abstract: An electrically conductive lead is formed using a bonding tool. After bonding the wire to a metal surface and extending a length of the wire beyond the bonding tool, the wire is clamped. Movement of the bonding tool imparts a kink to the wire at a location where the wire is fully separated from any metal element other than the bonding tool. A forming element, e.g., an edge or a blade skirt provided at an exterior surface of the bonding tool can help kink the wire. Optionally, twisting the wire while tensioning the wire using the bonding tool can cause the wire to break and define an end. The lead then extends from the metal surface to the end, and may exhibit a sign of the torsional force applied thereto.

公开(公告)号：US09893030B2

公开(公告)日：2018-02-13

申请号：US15212603

申请日：2016-07-18

Applicant: Invensas Corporation

Inventor： Cyprian Emeka Uzoh ,  Belgacem Haba ,  Charles G. Woychik ,  Michael Newman ,  Terrence Caskey

IPC: H05K7/00 ,  H01L23/00 ,  H05K1/18 ,  H05K3/30 ,  H01L25/065 ,  H01L25/00 ,  H01L21/56

CPC classification number: H01L24/13 ,  H01L21/563 ,  H01L23/564 ,  H01L24/02 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/14 ,  H01L24/16 ,  H01L24/17 ,  H01L24/32 ,  H01L24/81 ,  H01L24/83 ,  H01L24/92 ,  H01L25/0652 ,  H01L25/0655 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/02372 ,  H01L2224/0345 ,  H01L2224/03462 ,  H01L2224/03464 ,  H01L2224/0347 ,  H01L2224/03912 ,  H01L2224/03914 ,  H01L2224/0401 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05557 ,  H01L2224/05568 ,  H01L2224/05571 ,  H01L2224/05609 ,  H01L2224/05611 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05657 ,  H01L2224/05664 ,  H01L2224/10145 ,  H01L2224/1146 ,  H01L2224/11462 ,  H01L2224/11464 ,  H01L2224/1147 ,  H01L2224/11903 ,  H01L2224/13024 ,  H01L2224/13025 ,  H01L2224/13109 ,  H01L2224/13111 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13157 ,  H01L2224/13164 ,  H01L2224/1319 ,  H01L2224/14517 ,  H01L2224/1601 ,  H01L2224/16057 ,  H01L2224/16058 ,  H01L2224/16104 ,  H01L2224/16105 ,  H01L2224/16145 ,  H01L2224/16146 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/16503 ,  H01L2224/17505 ,  H01L2224/17517 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/81001 ,  H01L2224/81007 ,  H01L2224/811 ,  H01L2224/81139 ,  H01L2224/8192 ,  H01L2224/83104 ,  H01L2224/9201 ,  H01L2224/9212 ,  H01L2225/06513 ,  H01L2225/06524 ,  H01L2225/06541 ,  H01L2924/00014 ,  H05K1/181 ,  H05K3/30 ,  Y10T29/4913 ,  H01L2924/00012 ,  H01L2924/01015 ,  H01L2924/01074 ,  H01L2224/05552

Abstract: Microelectronic assemblies and methods for making the same are disclosed herein. In one embodiment, a method of forming a microelectronic assembly comprises assembling first and second components to have first major surfaces of the first and second components facing one another and spaced apart from one another by a predetermined spacing, the first component having first and second oppositely-facing major surfaces, a first thickness extending in a first direction between the first and second major surfaces, and a plurality of first metal connection elements at the first major surface, the second component having a plurality of second metal connection elements at the first major surface of the second component; and plating a plurality of metal connector regions each connecting and extending continuously between a respective first connection element and a corresponding second connection element opposite the respective first connection element in the first direction.

公开(公告)号：US09887166B2

公开(公告)日：2018-02-06

申请号：US15165837

申请日：2016-05-26

Applicant: Invensas Corporation

Inventor： Rajesh Katkar ,  Laura Wills Mirkarimi ,  Arkalgud R. Sitaram ,  Charles G. Woychik

IPC: H01L23/538 ,  H01L23/00 ,  H01L25/065 ,  H01L23/367 ,  H01L21/66 ,  H01L21/78 ,  H01L23/10 ,  H01L23/14 ,  H01L23/498 ,  H01L25/00 ,  H01L21/56 ,  H01L23/31 ,  H01L23/04 ,  H01L21/784 ,  H01L25/18

CPC classification number: H01L23/562 ,  H01L21/561 ,  H01L21/78 ,  H01L21/784 ,  H01L22/32 ,  H01L23/04 ,  H01L23/10 ,  H01L23/147 ,  H01L23/3121 ,  H01L23/3135 ,  H01L23/367 ,  H01L23/3675 ,  H01L23/49827 ,  H01L23/49838 ,  H01L24/05 ,  H01L24/06 ,  H01L24/09 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L24/17 ,  H01L24/32 ,  H01L24/73 ,  H01L24/83 ,  H01L24/92 ,  H01L24/94 ,  H01L24/97 ,  H01L25/0652 ,  H01L25/0655 ,  H01L25/0657 ,  H01L25/18 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/05568 ,  H01L2224/05569 ,  H01L2224/0603 ,  H01L2224/06181 ,  H01L2224/131 ,  H01L2224/1403 ,  H01L2224/14181 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/16238 ,  H01L2224/17181 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/83192 ,  H01L2224/92125 ,  H01L2224/92225 ,  H01L2224/94 ,  H01L2224/97 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06548 ,  H01L2225/06586 ,  H01L2225/06589 ,  H01L2225/06596 ,  H01L2924/12042 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/1615 ,  H01L2924/16152 ,  H01L2924/16153 ,  H01L2924/16176 ,  H01L2924/16235 ,  H01L2924/16251 ,  H01L2924/1632 ,  H01L2924/164 ,  H01L2924/167 ,  H01L2924/16788 ,  H01L2924/1679 ,  H01L2924/181 ,  H01L2924/351 ,  H01L2924/3511 ,  H01L2224/81 ,  H01L2224/83 ,  H01L2924/014 ,  H01L2924/00 ,  H01L2924/00012

Abstract: An assembly with modules (110, 1310) containing integrated circuits and attached to a wiring substrate (120) is reinforced by one or more reinforcement frames (410) attached to the wiring substrate. The modules are located in openings (e.g. cavities and/or through-holes 414) in the reinforcement frame. Other features are also provided.

公开(公告)号：US20180026019A1

公开(公告)日：2018-01-25

申请号：US15393112

申请日：2016-12-28

Applicant: Invensas Corporation

Inventor： Min Tao ,  Hoki Kim ,  Ashok S. Prabhu ,  Zhuowen Sun ,  Wael Zohni ,  Belgacem Haba

IPC: H01L25/10 ,  H01L25/00 ,  H01L21/48 ,  H01L21/56 ,  H01L23/538 ,  H01L23/31

CPC classification number: H01L25/0657 ,  H01L21/4853 ,  H01L21/4857 ,  H01L21/486 ,  H01L21/52 ,  H01L21/565 ,  H01L23/3114 ,  H01L23/3128 ,  H01L23/3157 ,  H01L23/5283 ,  H01L23/5383 ,  H01L23/5384 ,  H01L23/5386 ,  H01L23/5389 ,  H01L24/02 ,  H01L24/09 ,  H01L24/46 ,  H01L24/49 ,  H01L24/83 ,  H01L25/0652 ,  H01L25/071 ,  H01L25/105 ,  H01L25/112 ,  H01L25/18 ,  H01L25/50 ,  H01L2224/02331 ,  H01L2224/02379 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/16235 ,  H01L2224/32225 ,  H01L2225/06506 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06544 ,  H01L2225/06548 ,  H01L2225/06555 ,  H01L2225/06589 ,  H01L2225/1023 ,  H01L2225/1035 ,  H01L2225/1041 ,  H01L2225/1052 ,  H01L2225/1058 ,  H01L2225/1088 ,  H01L2924/15151 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/18161 ,  H01L2924/19107

Abstract: Package-on-package (“PoP”) devices with WLP (“WLP”) components with dual RDLs (“RDLs”) for surface mount dies and methods therefor. In a PoP, a first IC die surface mount coupled to an upper surface of a package substrate. Conductive lines are coupled to the upper surface of the package substrate in a fan-out region. A molding layer is formed over the upper surface of the package substrate. A first and a second WLP microelectronic component are located at a same level above an upper surface of the molding layer respectively surface mount coupled to sets of upper portions of the conductive lines. Each of the first and the second WLP microelectronic components have a second IC die located between a first RDL and a second RDL. A third and a fourth IC die are respectively surface mount coupled over the first and the second WLP microelectronic components.

公开(公告)号：US20180026017A1

公开(公告)日：2018-01-25

申请号：US15393068

申请日：2016-12-28

Applicant: Invensas Corporation

Inventor： Min Tao ,  Hoki Kim ,  Ashok S. Prabhu ,  Zhuowen Sun ,  Wael Zohni ,  Belgacem Haba

IPC: H01L25/10 ,  H01L23/31 ,  H01L25/00 ,  H01L21/48 ,  H01L21/56 ,  H01L23/538 ,  H01L25/18

CPC classification number: H01L25/0657 ,  H01L21/4853 ,  H01L21/4857 ,  H01L21/486 ,  H01L21/52 ,  H01L21/565 ,  H01L23/3114 ,  H01L23/3128 ,  H01L23/3157 ,  H01L23/5283 ,  H01L23/5383 ,  H01L23/5384 ,  H01L23/5386 ,  H01L23/5389 ,  H01L24/02 ,  H01L24/09 ,  H01L24/46 ,  H01L24/49 ,  H01L24/83 ,  H01L25/0652 ,  H01L25/071 ,  H01L25/105 ,  H01L25/112 ,  H01L25/18 ,  H01L25/50 ,  H01L2224/02331 ,  H01L2224/02379 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/16235 ,  H01L2224/32225 ,  H01L2225/06506 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06544 ,  H01L2225/06548 ,  H01L2225/06555 ,  H01L2225/06589 ,  H01L2225/1023 ,  H01L2225/1035 ,  H01L2225/1041 ,  H01L2225/1052 ,  H01L2225/1058 ,  H01L2225/1088 ,  H01L2924/15151 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/18161 ,  H01L2924/19107

Abstract: Dies-on-package devices and methods therefor are disclosed. In a dies-on-package device, a first IC die is surface mount coupled to an upper surface of a package substrate. Conductive lines are coupled to the upper surface of the package substrate in a fan-out region with respect to the first IC die. A molding layer is formed over the upper surface of the package substrate, around sidewall surfaces of the first IC die, and around bases and shafts of the conductive lines. A plurality of second IC dies is located at a same level above an upper surface of the molding layer respectively surface mount coupled to sets of upper portions of the conductive lines. The plurality of second IC dies are respectively coupled to the sets of the conductive lines in middle third portions respectively of the plurality of second IC dies for corresponding fan-in regions thereof.

公开(公告)号：US20180026016A1

公开(公告)日：2018-01-25

申请号：US15393119

申请日：2016-12-28

Applicant: Invensas Corporation

Inventor： Min Tao ,  Hoki Kim ,  Ashok S. Prabhu ,  Zhuowen Sun ,  Wael Zohni ,  Belgacem Haba

IPC: H01L25/07 ,  H01L25/00 ,  H01L23/31 ,  H01L23/00 ,  H01L23/528 ,  H01L25/11

CPC classification number: H01L25/0657 ,  H01L21/4853 ,  H01L21/4857 ,  H01L21/486 ,  H01L21/52 ,  H01L21/565 ,  H01L23/3114 ,  H01L23/3128 ,  H01L23/3157 ,  H01L23/5283 ,  H01L23/5383 ,  H01L23/5384 ,  H01L23/5386 ,  H01L23/5389 ,  H01L24/02 ,  H01L24/09 ,  H01L24/46 ,  H01L24/49 ,  H01L24/83 ,  H01L25/0652 ,  H01L25/071 ,  H01L25/105 ,  H01L25/112 ,  H01L25/18 ,  H01L25/50 ,  H01L2224/02331 ,  H01L2224/02379 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/16235 ,  H01L2224/32225 ,  H01L2225/06506 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06544 ,  H01L2225/06548 ,  H01L2225/06555 ,  H01L2225/06589 ,  H01L2225/1023 ,  H01L2225/1035 ,  H01L2225/1041 ,  H01L2225/1052 ,  H01L2225/1058 ,  H01L2225/1088 ,  H01L2924/15151 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/18161 ,  H01L2924/19107

Abstract: Package-on-package (“PoP”) devices with upper RDLs of WLP (“WLP”) components and methods therefor are disclosed. In a PoP device, a first IC die is surface mount coupled to an upper surface of the package substrate. Conductive lines are coupled to the upper surface of the package substrate in a fan-out region with reference to the first IC. A molding layer is formed over the upper surface of the package substrate. A first and a second WLP microelectronic component is located at a same level above an upper surface of the molding layer respectively surface mount coupled to sets of upper portions of the conductive lines. Each of the first and the second WLP microelectronic components have a second IC die located below a first RDL respectively thereof. A third and a fourth IC die are respectively surface mount coupled over the first and the second WLP microelectronic components.