公开(公告)号：US20100128442A1

公开(公告)日：2010-05-27

申请号：US12464519

申请日：2009-05-12

Applicant: ZHI-PING WU ,  XIAO-FENG WANG ,  YU-HSU LIN ,  JENG-DA WU ,  CHIH-HANG CHAO

Inventor： ZHI-PING WU ,  XIAO-FENG WANG ,  YU-HSU LIN ,  JENG-DA WU ,  CHIH-HANG CHAO

IPC: H05K7/20

CPC classification number: H01L23/4093 ,  H01L23/4006 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A heat sink assembly includes a printed circuit board, a socket attached on a top surface of the board for receiving a chip, and a heat sink attached onto the chip of the board. The socket includes a plurality of legs integrally extending down from a bottom surface of the socket. The legs contact the top surface of the board to support the socket on the board. The heat sink includes a base, a plurality of fins extending up from the base, and a plurality of legs extending down from the base.

Abstract translation: 散热器组件包括印刷电路板，安装在用于接收芯片的板的顶表面上的插座和附接到板的芯片上的散热器。 插座包括从插座的底表面向下整体延伸的多个脚。 腿接触板的顶面以支撑板上的插座。 散热器包括基座，从基座向上延伸的多个翅片以及从基座向下延伸的多个腿部。

公开(公告)号：US20100096170A1

公开(公告)日：2010-04-22

申请号：US12645303

申请日：2009-12-22

Applicant: YU-HSU LIN ,  JENG-DA WU ,  CHIH-HANG CHAO

Inventor： YU-HSU LIN ,  JENG-DA WU ,  CHIH-HANG CHAO

IPC: H05K1/02 ,  H05K3/10

CPC classification number: H01L23/50 ,  H01L23/49838 ,  H01L2924/0002 ,  H01L2924/3011 ,  H05K1/0224 ,  H05K1/0253 ,  H05K2201/09281 ,  H05K2201/09681 ,  Y10T29/49128 ,  Y10T29/49147 ,  Y10T29/49155 ,  H01L2924/00

Abstract: A circuit board includes a signal plane and a ground plane. The signal plane is configured to have a plurality of signal traces arranged thereon. Each of the signal traces includes a plurality of straight line segments. Each line segment extends along a path different from the others. The ground plane includes a plurality of tiles connected in an array. Each tile is formed by ground traces. The straight line segments of each signal trace mapped on the ground plane are arranged at an angle relative to any one ground trace of the tiles. The angle is defined within a range determined by one of ground traces of a tile and an adjacent diagonal line of the tile. A method for laying out such a circuit board is also provided.

Abstract translation: 电路板包括信号平面和接地平面。 信号平面被配置为具有布置在其上的多个信号迹线。 每个信号迹线包括多个直线段。 每个线段沿着与其他线不同的路径延伸。 接地平面包括以阵列连接的多个瓦。 每个瓷砖由地面痕迹形成。 映射在接地平面上的每个信号迹线的直线段相对于瓦片的任何一个接地迹线以一定角度布置。 该角度限定在由瓦片的接地轨迹和瓦片的相邻对角线之一确定的范围内。 还提供了布线这种电路板的方法。

公开(公告)号：US20090171604A1

公开(公告)日：2009-07-02

申请号：US12124782

申请日：2008-05-21

Applicant: YU-HSU LIN ,  JENG-DA WU ,  CHIH-HANG CHAO

Inventor： YU-HSU LIN ,  JENG-DA WU ,  CHIH-HANG CHAO

IPC: G01R27/06 ,  G01R27/32

CPC classification number: G01R27/32 ,  G01R35/00

Abstract: The invention related to a method and circuit that is used to compensate for S-parameters of a passive circuit which do not satisfy passivity. The method includes the following steps: (1) getting S-parameters which do not satisfy passivity, these S-parameters being composed of an S-parameter matrix S; (2) computing matrix [S×S′], wherein matrix S′ is a complex conjugate transposed matrix of the S-parameter matrix S; (3) computing the eigenvalues of the matrix [S×S′], and choosing an eigenvalue Ψ whose real part real(Ψ) is the biggest; (4) computing a compensating value ξ, the compensating value ξ being equal to real(Ψ)1/2×(1+ε), wherein the ε is a very small positive number; and (5) dividing each of the S-parameters by the compensating value ξ to get the compensated S-parameters.

Abstract translation: 本发明涉及一种用于补偿不满足被动无源电路的S参数的方法和电路。 该方法包括以下步骤：（1）获得不满足被动的S参数，这些S参数由S参数矩阵S组成; （2）计算矩阵[SxS']，其中矩阵S'是S参数矩阵S的复共轭转置矩阵; （3）计算矩阵[SxS']的特征值，并选择其实部实数（Psi）最大的特征值Psi; （4）计算补偿值xi，补偿值xi等于实数（Psi）1 / 2x（1 +ε），其中ε是非常小的正数; 和（5）将每个S参数除以补偿值xi以获得经补偿的S参数。

公开(公告)号：US20090168361A1

公开(公告)日：2009-07-02

申请号：US12180221

申请日：2008-07-25

Applicant: CHIH-HANG CHAO ,  YU-HSU LIN ,  JENG-DA WU ,  LEI GUO

Inventor： CHIH-HANG CHAO ,  YU-HSU LIN ,  JENG-DA WU ,  LEI GUO

IPC: H05K7/20

CPC classification number: H01L23/367 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A printed circuit board assembly includes a printed circuit board with a heat generating component attached thereon, a base, and a thermal plate. The heat generating component comprises a side surface. The base defines a receiving room and an opening configured for access into the receiving room. The printed circuit board is received in the receiving room via the opening. The thermal plate is mounted on the base to cover the opening. A conducting piece is formed on the thermal plate and extends into the receiving room. The conducting piece includes a contacting portion extending from the thermal plate and in contact with the side surface. The conducting piece is configured for conducting heat from the heat generating component to the thermal plate. A heat dissipating hole is defined on the thermal plate in alignment with the contacting portion configured for dissipating heat from the base.

Abstract translation: 印刷电路板组件包括其上附着有发热元件的印刷电路板，基座和热敏板。 发热部件包括侧面。 基座定义了接收室和被配置为进入接收室的开口。 印刷电路板通过开口接收在接收室中。 热板安装在基座上以覆盖开口。 导热片形成在热板上并延伸到接收室。 导电件包括从热板延伸并与侧表面接触的接触部分。 导电件构造成用于将热量从发热部件传导到热板。 在热板上限定散热孔，该散热孔与构造成从底部散热的接触部分对齐。

公开(公告)号：US20090166062A1

公开(公告)日：2009-07-02

申请号：US12118684

申请日：2008-05-10

Applicant: ZHI-PING WU ,  JENG-DA WU ,  YU-HSU LIN ,  CHIH-HANG CHAO ,  LIANG-LIANG CAO

Inventor： ZHI-PING WU ,  JENG-DA WU ,  YU-HSU LIN ,  CHIH-HANG CHAO ,  LIANG-LIANG CAO

IPC: H05K1/00

CPC classification number: H01L23/367 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A printed circuit board assembly includes a printed circuit board, a carrier, a semiconductor chip mounted on the carrier, a plurality of tin balls soldered between the printed circuit board and the carrier for transmitting signals, and a heat sink glued to the semiconductor chip to dissipate heat. A pressing portion is formed on the bottom of the heat sink and does not make contact with the semiconductor chip. The pressing portion contacts with the periphery of the carrier to reinforce the tin balls located between the printed circuit board and the carrier.

Abstract translation: 印刷电路板组件包括印刷电路板，载体，安装在载体上的半导体芯片，焊接在印刷电路板和用于传输信号的载体之间的多个锡球，以及胶合到半导体芯片的散热片 散热 在散热器的底部形成有按压部，不与半导体芯片接触。 按压部分与载体的周边接触以加强位于印刷电路板和载体之间的锡球。

公开(公告)号：US07447014B2

公开(公告)日：2008-11-04

申请号：US11309778

申请日：2006-09-23

Applicant: Chih-Hang Chao ,  Yu-Hsu Lin ,  Jeng-Da Wu ,  Zhi-Ping Wu

Inventor： Chih-Hang Chao ,  Yu-Hsu Lin ,  Jeng-Da Wu ,  Zhi-Ping Wu

IPC: H05K7/00

CPC classification number: G06F1/187

Abstract: A bracket assembly for receiving at least one disk drive (40) includes an enclosure (10), a retaining bracket (30), and a connecting structure (312). The retaining bracket includes a pair of sidewalls (31, 32). The retaining bracket is attached to the enclosure at an edge of each sidewall. The connecting structure is defined in a first sidewall (31) of the sidewalls for attaching the first sidewall to the enclosure for altering a fixing relationship between the retaining bracket and the enclosure. The connecting structure is positioned near the disk drive, and away from the edge of the first sidewall. The method of assembling the bracket (30) to the enclosure (10) is also provided.

Abstract translation: 用于容纳至少一个盘驱动器（40）的支架组件包括外壳（10），固定支架（30）和连接结构（312）。 保持支架包括一对侧壁（31,32）。 保持支架在每个侧壁的边缘附接到外壳。 连接结构限定在侧壁的第一侧壁（31）中，用于将第一侧壁附接到外壳以改变保持支架和外壳之间的固定关系。 连接结构位于盘驱动器附近，并远离第一侧壁的边缘。 还提供了将支架（30）组装到外壳（10）的方法。

公开(公告)号：US07335982B2

公开(公告)日：2008-02-26

申请号：US10907340

申请日：2005-03-30

Applicant: Chin-Li Kao ,  Yi-Shao Lai ,  Jeng-Da Wu ,  Tong-Hong Wang

Inventor： Chin-Li Kao ,  Yi-Shao Lai ,  Jeng-Da Wu ,  Tong-Hong Wang

IPC: H01L23/10

CPC classification number: H01L23/36 ,  H01L23/13 ,  H01L23/3128 ,  H01L24/48 ,  H01L24/73 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2924/00014 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/15153 ,  H01L2924/1517 ,  H01L2924/15311 ,  H01L2924/1532 ,  H01L2924/181 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A chip packaging process is provided. First, a cavity is formed on a heat sink. A first encapsulant is formed on the bottom of the cavity. A circuit substrate is disposed over the heat sink. The circuit substrate has an opening that corresponds in position to the cavity. Thereafter, a chip is disposed on the first encapsulant and the chip is electrically connected to the circuit substrate. Finally, a compound is deposited over the first encapsulant and the chip to form a chip package. The chip package is warp resistant and the chip packaging process increases overall production yield.

Abstract translation: 提供了芯片封装工艺。 首先，在散热器上形成空腔。 第一密封剂形成在空腔的底部。 电路基板设置在散热器的上方。 电路基板具有与空腔相对应的开口。 此后，芯片设置在第一密封剂上，并且芯片电连接到电路基板。 最后，化合物沉积在第一密封剂和芯片上以形成芯片封装。 芯片封装具有抗扭性，芯片封装工艺提高了整体生产成本。

公开(公告)号：US07199479B2

公开(公告)日：2007-04-03

申请号：US10907400

申请日：2005-03-31

Applicant: Jeng-Da Wu

Inventor： Jeng-Da Wu

IPC: H01L23/28 ,  H01L23/29

CPC classification number: H01L21/563 ,  H01L23/3128 ,  H01L2224/05001 ,  H01L2224/05022 ,  H01L2224/05572 ,  H01L2224/1147 ,  H01L2224/1148 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73203 ,  H01L2224/73204 ,  H01L2924/00013 ,  H01L2924/00014 ,  H01L2924/01019 ,  H01L2924/15311 ,  H01L2924/00 ,  H01L2224/29099 ,  H01L2224/05599 ,  H01L2224/05099

Abstract: A chip package structure comprises a carrier, a chip and an underfill. The chip has an active surface on which a plurality of bumps are formed. The chip is flip-chip bonded onto the carrier with the active surface facing the carrier, and is electrically connected to the carrier through the bumps. The underfill is filled between the chip and the carrier. A portion of the underfill near the chip serves as a first underfill portion. The portion of the underfill near the carrier serves as a second underfill portion. The Young's modulus of the first underfill portion is smaller than the Young's modulus of the second underfill portion. The second underfill portion can be optionally replaced with a selected encapsulation. The selected encapsulation covers the chip and the carrier around the chip.

Abstract translation: 芯片封装结构包括载体，芯片和底部填充物。 芯片具有形成有多个凸起的活性表面。 该芯片以有源表面面向载体的方式倒装芯片结合到载体上，并通过凸块与载体电连接。 底部填充物填充在芯片和载体之间。 芯片附近的一部分底部填充物用作第一底部填充部分。 载体附近的底部填充部分用作第二底部填充部分。 第一底部填充部分的杨氏模量小于第二底部填充部分的杨氏模量。 第二底部填充部分可以任选地用选择的封装代替。 所选择的封装覆盖芯片周围的芯片和载体。

公开(公告)号：US07042078B2

公开(公告)日：2006-05-09

申请号：US10776227

申请日：2004-02-12

Applicant: Jeng Da Wu

Inventor： Jeng Da Wu

IPC: H01L23/52

CPC classification number: H01L24/32 ,  H01L23/3107 ,  H01L23/3128 ,  H01L23/49575 ,  H01L24/48 ,  H01L24/73 ,  H01L25/0652 ,  H01L25/0657 ,  H01L2224/05599 ,  H01L2224/16225 ,  H01L2224/16245 ,  H01L2224/17181 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/45099 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48247 ,  H01L2224/73207 ,  H01L2224/73257 ,  H01L2224/73265 ,  H01L2224/83138 ,  H01L2224/85399 ,  H01L2225/0651 ,  H01L2225/06517 ,  H01L2225/06565 ,  H01L2225/06568 ,  H01L2225/06575 ,  H01L2924/00014 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01082 ,  H01L2924/15153 ,  H01L2924/15165 ,  H01L2924/15311 ,  H01L2924/1532 ,  H01L2924/181 ,  H01L2924/1815 ,  H01L2924/19041 ,  H01L2924/351 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A semiconductor package includes spacers, a chip, bonding wires, contacts, and an encapsulant. The chip is disposed on the spacers. The bonding wires are electrically connected to the chip, and the contacts are electrically connected to the bonding wires. The contacts are electrically connected to an external circuit board. The encapsulant encapsulates the spacers and the active and back surfaces of the chip so as to lower the thermal stress of the chip.

Abstract translation: 半导体封装包括间隔物，芯片，接合线，触点和密封剂。 芯片设置在间隔物上。 接合线电连接到芯片，并且触点电连接到接合线。 触点电连接到外部电路板。 密封剂封装了间隔物和芯片的有源和背面，以降低芯片的热应力。

公开(公告)号：US20050275098A1

公开(公告)日：2005-12-15

申请号：US11151755

申请日：2005-06-14

Applicant: Jeng-Da Wu

Inventor： Jeng-Da Wu

IPC: H01L21/60 ,  H01L23/48 ,  H01L23/485 ,  H01L23/52 ,  H01L29/40

CPC classification number: H01L24/13 ,  H01L24/11 ,  H01L2224/05001 ,  H01L2224/05022 ,  H01L2224/05124 ,  H01L2224/05166 ,  H01L2224/05171 ,  H01L2224/05572 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/13099 ,  H01L2224/13111 ,  H01L2924/0001 ,  H01L2924/01013 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/15787 ,  H01L2924/00014 ,  H01L2924/00

Abstract: A conductive jointing structure that is applied on a chip with multitude of connection pads has a first conductive structure and a second conductive structure. The first conductive structure is allocated on one of the contact pads. The second conductive structure made of lead-free based material is consisted of multitude of stacked portions with respectively different modulus. The portion contacting the first conductive structure is with small modulus, while the portion away from the first conductive structure is with large modulus.

Abstract translation: 施加在具有多个连接焊盘的芯片上的导电接合结构具有第一导电结构和第二导电结构。 第一导电结构分配在一个接触垫上。 由无铅基材料制成的第二导电结构由分别具有不同模量的多个堆叠部分组成。 与第一导电结构接触的部分具有小的模量，而远离第一导电结构的部分具有大的模量。