公开(公告)号：US07667289B2

公开(公告)日：2010-02-23

申请号：US11091508

申请日：2005-03-29

Applicant: Jian-Hong Lin ,  Kang-Cheng Lin

Inventor： Jian-Hong Lin ,  Kang-Cheng Lin

IPC: H01L21/326

CPC classification number: H01L23/5258 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A laser fuse structure for a semiconductor device, the laser fuse structure having an array of laser fuses wherein one or more of the fuses in the array have a tortuous fuse line extending between first and second connectors that connect the fuse to an underlying circuit area.

Abstract translation: 一种用于半导体器件的激光熔丝结构，所述激光熔丝结构具有激光熔丝阵列，其中阵列中的一个或多个熔丝具有在将熔丝连接到下面的电路区域的第一和第二连接器之间延伸的曲折熔丝。

公开(公告)号：US20080251923A1

公开(公告)日：2008-10-16

申请号：US11786076

申请日：2007-04-10

Applicant: Chien-Jung Wang ,  Jian-Hong Lin

Inventor： Chien-Jung Wang ,  Jian-Hong Lin

IPC: H01L23/522 ,  H01L29/06

CPC classification number: H01L23/585 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor chip includes a seal ring adjacent to edges of the semiconductor chip; an opening extending from a top surface to a bottom surface of the seal ring, wherein the opening has a first end on an outer side of the seal ring and a second end on an inner side of the seal ring; and a moisture barrier having a sidewall parallel to a nearest side of the seal ring, wherein the moisture barrier is adjacent the seal ring and has a portion facing the opening.

Abstract translation: 半导体芯片包括与半导体芯片的边缘相邻的密封环; 从所述密封环的顶表面延伸到底表面的开口，其中所述开口具有在所述密封环的外侧上的第一端和所述密封环的内侧上的第二端; 以及具有平行于所述密封环的最近侧的侧壁的防潮屏障，其中所述防潮层邻近所述密封环并且具有面向所述开口的部分。

公开(公告)号：US20070015365A1

公开(公告)日：2007-01-18

申请号：US11181433

申请日：2005-07-14

Applicant: Hsien-Wei Chen ,  Hao-Yi Tsai ,  Hsueh-Chung Chen ,  Shin-Puu Jeng ,  Jian-Hong Lin ,  Chih-Tao Lin ,  Shih-Hsun Hsu

Inventor： Hsien-Wei Chen ,  Hao-Yi Tsai ,  Hsueh-Chung Chen ,  Shin-Puu Jeng ,  Jian-Hong Lin ,  Chih-Tao Lin ,  Shih-Hsun Hsu

IPC: H01L21/461

CPC classification number: H01L21/3212 ,  H01L21/31053

Abstract: In one embodiment, the disclosure relates to a method and apparatus for inserting dummy patterns in sparsely populated portions of a metal layer. The dummy pattern counters the effects of variations of pattern density in a semiconductor layout which can cause uneven post-polish film thickness. An algorithm according to one embodiment of the disclosure determines the size and location of the dummy patterns based on the patterns in the metal layer by first surrounding the metal structure with small dummy pattern and then filling any remaining voids with large dummy patterns.

公开(公告)号：US20060099787A1

公开(公告)日：2006-05-11

申请号：US10983681

申请日：2004-11-09

Applicant: Jian-Hong Lin ,  Ying-Jen Kao ,  Jye-Yen Cheng

Inventor： Jian-Hong Lin ,  Ying-Jen Kao ,  Jye-Yen Cheng

IPC: H01L21/44

CPC classification number: H01L21/76808

Abstract: Methods for forming openings in damascene structures, such as dual damascene structures are provided, using plug materials having varied etching rates. In one embodiment, a semiconductor substrate is provided with a low-k material layer formed thereabove, the low-k material layer having an upper surface and at least one via opening formed therethrough. A first plug material layer is formed over the low-k material layer and filled in the via opening, the first plug material layer having a first etching rate. The first plug material layer is etched back to form a first plug partially filling the via opening. A second plug material layer is formed over the low-k material layer and the first plug. The second plug material layer is etched back to form a second plug partially below the upper surface of the low-k material layer, the second plug material layer having a second etching rate higher than the first etching rate.