公开(公告)号：US20050079686A1

公开(公告)日：2005-04-14

申请号：US10921087

申请日：2004-08-18

Applicant: Robert Aigner ,  Martin Franosch ,  Andreas Meckes ,  Klaus-Guenter Oppermann ,  Marc Strasser

Inventor： Robert Aigner ,  Martin Franosch ,  Andreas Meckes ,  Klaus-Guenter Oppermann ,  Marc Strasser

IPC: H03H9/10 ,  H01L21/00 ,  H01L21/30 ,  H01L21/48

CPC classification number: H03H9/1071 ,  H03H9/105

Abstract: In a method for producing a cover for a region of a substrate, first a frame structure is produced in the region of the substrate, and then a cap structure is attached to the frame structure so that the region under the cap structure is covered. Thus, sensitive devices may be protected easily and at low cost from external influences and particularly from a casting material for casting the entire packaged device, which results when a diced chip is cast.

Abstract translation: 在用于制造基板区域的盖的方法中，首先在基板的区域中制造框架结构，然后将盖结构附接到框架结构，使得盖结构下方的区域被覆盖。 因此，敏感装置可以容易地以低成本保护外部影响，特别是用于铸造整个封装装置的铸造材料，这在铸造切割的芯片时产生。

公开(公告)号：US06878600B2

公开(公告)日：2005-04-12

申请号：US10436426

申请日：2003-05-12

Applicant: Albert Birner ,  Matthias Goldbach ,  Martin Franosch

Inventor： Albert Birner ,  Matthias Goldbach ,  Martin Franosch

IPC: H01L21/3063 ,  H01L21/8242 ,  H01L27/108 ,  H01L21/20

CPC classification number: H01L27/1087

Abstract: A method for fabricating trench capacitors having trenches with mesopores, the trench capacitors being suitable both for discrete capacitors and for integrated semiconductor memories, significantly increases the surface area for electrodes of the capacitors and, hence, the capacitance thereof. The mesopores, which are small woodworm-hole-like channels having diameters from approximately 2 to 50 nm, are fabricated electrochemically. It is, thus, possible to produce capacitances with a large capacitance-to-volume ratio. Growth of the mesopores stops, at the latest, when the mesopores reach a minimum distance from another mesopore or adjacent trench (self-passivation). As such, the formation of “short circuits” between two adjacent mesopores can be avoided in a self-regulated manner. Furthermore, a semiconductor device is provided including at least one trench capacitor on the front side of a semiconductor substrate fabricated by the method according to the invention.

Abstract translation: 一种用于制造具有中孔的沟槽的沟槽电容器的方法，所述沟槽电容器适用于分立电容器和集成半导体存储器，显着增加了电容器的电极的表面积，并因此显着增加了其电容。 电化学地制造直径为约2〜50nm的小木蛾孔状通道的中孔。 因此，可以产生具有大的电容容积比的电容。 当介孔达到与另一个中孔或相邻沟槽的最小距离（自钝化）时，介孔的生长最终停止。 因此，可以以自我调节的方式避免在两个相邻介孔之间形成“短路”。 此外，提供一种半导体器件，其包括通过根据本发明的方法制造的半导体衬底的前侧上的至少一个沟槽电容器。

公开(公告)号：US20050009316A1

公开(公告)日：2005-01-13

申请号：US10820652

申请日：2004-04-08

Applicant: Martin Franosch ,  Andreas Meckes ,  Klaus-Gunter Oppermann

Inventor： Martin Franosch ,  Andreas Meckes ,  Klaus-Gunter Oppermann

IPC: B81B7/00 ,  H03H3/007 ,  H03H9/02 ,  H01L21/44

CPC classification number: B81C1/00333 ,  B81C2203/0136 ,  H01L2224/11 ,  H03H3/007 ,  H03H9/02834 ,  H03H9/02984

Abstract: In a method for producing a protective cover for a device which is formed in a substrate, a first cover layer is initially deposited on the substrate, the first cover layer covering an area of the substrate which includes the device. Subsequently, an opening is formed in the first cover layer, the opening exposing that area of the substrate which includes the device. Then the opening formed in the first cover layer is filled up using a filling material. Subsequently, a second cover layer is deposited on the first cover layer and in the opening of the first cover layer which is filled up with the filling material. Thereafter, an opening is formed in the second cover layer to expose an area of the filling material. Finally, the filling material covering that area of the substrate which includes the device is removed, and the opening formed in the second cover layer is closed.

公开(公告)号：US06605487B2

公开(公告)日：2003-08-12

申请号：US10027044

申请日：2001-12-20

Applicant: Martin Franosch ,  Reinhard Wittmann ,  Catharina Pusch

Inventor： Martin Franosch ,  Reinhard Wittmann ,  Catharina Pusch

IPC: H01L2100

CPC classification number: B81C1/00476 ,  B81C1/00047 ,  B81C2201/016

Abstract: A method for the manufacture of micro-mechanical components from a stack of layers having at least a substrate, a sacrificial layer and a layer which is to be undercut includes forming at least one etch hole in the layer, which is to be undercut, and providing at least one passivation layer for controlling a selective depositing of a cover material which closes each of the etch holes after a step of etching the sacrificial layer. The passivation layer makes it possible that the undercut layer elements do not become excessively thick or grow together with the substrate due to the deposition of the cover material.

公开(公告)号：US06552385B2

公开(公告)日：2003-04-22

申请号：US09756082

申请日：2001-01-08

Applicant: Gerhard Beitel ,  Martin Franosch ,  Thomas Peter Haneder ,  Gerrit Lange ,  Hans Reisinger ,  Herbert Schäfer ,  Stephan Schlamminger ,  Hermann Wendt

Inventor： Gerhard Beitel ,  Martin Franosch ,  Thomas Peter Haneder ,  Gerrit Lange ,  Hans Reisinger ,  Herbert Schäfer ,  Stephan Schlamminger ,  Hermann Wendt

IPC: H01L27108

CPC classification number: H01L28/56 ,  H01L21/02197 ,  H01L21/02266 ,  H01L21/31691

Abstract: A DRAM capacitor is described that contains a BaSrTiO3 (BST) dielectric. The dielectric has a three-layer structure enabling the formation of a potential trough in which electrons can be permanently trapped.

Abstract translation: 描述了包含BaSrTiO 3（BST）电介质的DRAM电容器。 该电介质具有能够形成电子槽的三层结构，其中电子可以永久性地被捕获。

公开(公告)号：US06215140B1

公开(公告)日：2001-04-10

申请号：US09398691

申请日：1999-09-20

Applicant: Hans Reisinger ,  Martin Franosch ,  Herbert Schäfer ,  Reinhard Stengl ,  Volker Lehmann ,  Gerrit Lange ,  Hermann Wendt

Inventor： Hans Reisinger ,  Martin Franosch ,  Herbert Schäfer ,  Reinhard Stengl ,  Volker Lehmann ,  Gerrit Lange ,  Hermann Wendt

IPC: H01L2972

CPC classification number: H01L21/8229 ,  H01L27/1021

Abstract: A memory cell configuration in a semiconductor substrate is proposed, in which the semiconductor substrate is of the first conductivity type. Trenches which run parallel to one another are incorporated in the semiconductor substrate, and first address lines run along the side walls of the trenches. Second address lines are formed on the semiconductor substrate, transversely with respect to the trenches. Semiconductor substrate regions, in which a diode and a dielectric whose conductivity can be changed are arranged, are located between the first address lines and the second address lines. A suitable current pulse can be used to produce a breakdown in the dielectric, with information thus being stored in the dielectric.

Abstract translation: 提出半导体衬底中的存储单元结构，其中半导体衬底是第一导电类型。 相互平行延伸的沟槽并入半导体衬底中，并且第一地址线沿着沟槽的侧壁延伸。 第二地址线在半导体衬底上相对于沟槽横向地形成。 布置有可以改变导电性的二极管和电介质的半导体衬底区域位于第一地址线和第二地址线之间。 可以使用合适的电流脉冲来产生电介质中的击穿，由此将信息存储在电介质中。

公开(公告)号：US06197666B1

公开(公告)日：2001-03-06

申请号：US09390496

申请日：1999-09-03

Applicant: Herbert Schafer ,  Martin Franosch ,  Reinhard Stengl ,  Hans Reisinger ,  Matthias Ilg

Inventor： Herbert Schafer ,  Martin Franosch ,  Reinhard Stengl ,  Hans Reisinger ,  Matthias Ilg

IPC: H01L2120

CPC classification number: H01L27/10873 ,  C23C16/24 ,  C23C16/56 ,  H01L21/28035 ,  H01L21/32055 ,  H01L21/76877

Abstract: A method for the fabrication of a doped silicon layer, includes carrying out deposition by using a process gas containing SiH4, Si2H6 and a doping gas. The doped silicon layer which is thus produced can be used both as a gate electrode of an MOS transistor and as a conductive connection. At a thickness between 50 and 200 nm it has a resistivity less than or equal to 0.5 m&OHgr;cm.

Abstract translation: 一种用于制造掺杂硅层的方法，包括通过使用含有SiH 4，Si 2 H 6和掺杂气体的工艺气体进行沉积。 由此制造的掺杂硅层既可以用作MOS晶体管的栅电极，也可以用作导电连接。 在50至200nm的厚度之间，其电阻率小于或等于0.5mOMEGAcm。

公开(公告)号：US6133126A

公开(公告)日：2000-10-17

申请号：US398688

申请日：1999-09-20

Applicant: Hans Reisinger ,  Martin Franosch ,  Herbert Schafer ,  Reinhard Stengl ,  Volker Lehmann ,  Gerrit Lange ,  Hermann Wendt

Inventor： Hans Reisinger ,  Martin Franosch ,  Herbert Schafer ,  Reinhard Stengl ,  Volker Lehmann ,  Gerrit Lange ,  Hermann Wendt

IPC: H01L21/225 ,  H01L21/768 ,  H01L21/8239 ,  H01L27/105 ,  H01L21/22

CPC classification number: H01L21/76888 ,  H01L21/2256 ,  H01L27/105 ,  H01L27/1052

Abstract: A method for fabricating a dopant region is disclosed. The dopant region is formed by providing a semiconductor substrate that has a surface. An electrically insulating intermediate layer is applied to the surface. A doped semiconductor layer is then applied to the electrically insulating intermediate layer, the semiconductor layer being of a first conductivity type and contains a dopant of the first conductivity type. A temperature treatment of the semiconductor substrate at a predefined diffusion temperature is performed, so that the dopant diffuses partially out of the semiconductor layer through the intermediate layer into the semiconductor substrate and forms there a dopant region of the first conductivity type. The electrical conductivity of the intermediate layer is modified, so that an electrical contact between the semiconductor substrate and the semiconductor layer is produced through the intermediate layer.

Abstract translation: 公开了一种制造掺杂剂区域的方法。 通过提供具有表面的半导体衬底形成掺杂剂区域。 将电绝缘的中间层施加到表面。 然后将掺杂半导体层施加到电绝缘中间层，所述半导体层是第一导电类型并且包含第一导电类型的掺杂剂。 执行预定扩散温度下的半导体衬底的温度处理，使得掺杂剂从半导体层中部分扩散通过中间层进入半导体衬底，并在其上形成第一导电类型的掺杂区域。 改变中间层的导电性，从而通过中间层产生半导体衬底和半导体层之间的电接触。

公开(公告)号：US05998807A

公开(公告)日：1999-12-07

申请号：US925672

申请日：1997-09-09

Applicant: Bernhard Lustig ,  Herbert Schaefer ,  Martin Franosch

Inventor： Bernhard Lustig ,  Herbert Schaefer ,  Martin Franosch

IPC: H01L21/8238 ,  H01L21/8256 ,  H01L27/092 ,  H01L27/12 ,  H01L29/786 ,  H01L29/76

CPC classification number: H01L27/092 ,  H01L21/8256 ,  H01L27/1203

Abstract: Semiconductor islands respectively comprise at least a Si.sub.1-x Ge.sub.x layer and a distorted silicon layer that exhibits essentially the same lattice constant as the Si.sub.1-x Ge.sub.x layer are formed on an insulating layer that is located on a carrier plate. The semiconductor islands are preferably formed by selective epitaxy and comprise p-channel MOS transistors and/or n-channel MOS transistors.

Abstract translation: 半导体岛分别至少包含Si1-xGex层和在位于载体板上的绝缘层上形成与Si1-xGex层基本相同的晶格常数的失真硅层。 半导体岛优选通过选择性外延形成并且包括p沟道MOS晶体管和/或n沟道MOS晶体管。

公开(公告)号：US20110133188A1

公开(公告)日：2011-06-09

申请号：US13026326

申请日：2011-02-14

Applicant: Herbert Schäfer ,  Martin Franosch ,  Thomas Meister ,  Josef Böck

Inventor： Herbert Schäfer ,  Martin Franosch ,  Thomas Meister ,  Josef Böck

IPC: H01L29/06

CPC classification number: H01L21/02639 ,  H01L21/02532 ,  H01L21/02573 ,  H01L21/0262 ,  H01L21/02661

Abstract: One embodiment of the present invention relates to method for the concurrent deposition of multiple different crystalline structures on a semiconductor body utilizing in-situ differential epitaxy. In one embodiment of the present invention a preparation surface is formed, resulting in two distinct crystalline regions, a monocrystalline silicon substrate region and an isolating layer region. A monocrystalline silicon layer and an amorphous silicon layer are concurrently formed directly onto the preparation surface in the monocrystalline silicon substrate region and the isolating layer region, respectively. Deposition comprises the formation of two or more sub-layers. The process parameters can be varied for each individual sub-layer to optimize deposition characteristics.

Abstract translation: 本发明的一个实施例涉及利用原位差分外延在半导体主体上同时沉积多个不同结晶结构的方法。 在本发明的一个实施方案中，形成制备表面，得到两个不同的结晶区域，单晶硅衬底区域和隔离层区域。 单晶硅层和非晶硅层同时直接分布在单晶硅衬底区域和隔离层区域的制备表面上。 沉积包括形成两个或更多个子层。 可以为每个单独的子层改变工艺参数以优化沉积特性。