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    Semiconductor memory cell array having self-aligned recessed gate MOS transistors and method for forming the same
    1.
    发明申请
    Semiconductor memory cell array having self-aligned recessed gate MOS transistors and method for forming the same 审中-公开
    具有自对准凹栅MOS晶体管的半导体存储单元阵列及其形成方法

    公开(公告)号：US20070040202A1

    公开(公告)日：2007-02-22

    申请号：US11206306

    申请日：2005-08-18

    Applicant: Gerhard Enders ,  Marc Strasser ,  Peter Voigt ,  Bjorn Fischer

    Inventor： Gerhard Enders ,  Marc Strasser ,  Peter Voigt ,  Bjorn Fischer

    IPC: H01L29/94 ,  H01L21/8242

    CPC classification number: H01L27/10876 ,  H01L27/10861

    Abstract: In a semiconductor memory including an array of memory cells, each memory cell includes a trench capacitor, the trench capacitor including an inner electrode, an outer electrode and a dielectric layer disposed between the inner electrode and the outer electrode, and a selection transistor, the selection transistor including a first source/drain area, a second source/drain area and a channel region disposed between the first source/drain area and the second source/drain area in a recess, the trench capacitor and the selection transistor of each memory cell are disposed side by side, the first source/drain area of the selection transistor being electrically connected to the inner electrode of the trench capacitor, the recess in which the channel region of the selection transistor is formed being located self aligned between the trench capacitor of the memory cell and the trench capacitor of an adjacent memory cell.

    Abstract translation: 在包括存储单元阵列的半导体存储器中，每个存储单元包括沟槽电容器，所述沟槽电容器包括内电极，外电极和设置在内电极和外电极之间的电介质层，以及选择晶体管， 选择晶体管，其包括第一源极/漏极区域，第二源极/漏极区域和设置在凹部中的第一源极/漏极区域和第二源极/漏极区域之间的沟道区域，每个存储器单元的沟槽电容器和选择晶体管 并排配置，选择晶体管的第一源极/漏极区域电连接到沟槽电容器的内部电极，形成选择晶体管的沟道区域的凹槽位于沟槽电容器的沟槽电容器之间， 存储单元和相邻存储单元的沟槽电容器。

    Integrated circuit device and method of manufacture
    2.
    发明授权
    Integrated circuit device and method of manufacture 失效
    集成电路器件及其制造方法

    公开(公告)号：US07763513B2

    公开(公告)日：2010-07-27

    申请号：US11222540

    申请日：2005-09-09

    Applicant: Peng-Fei Wang ,  Joachim Nuetzel ,  Rolf Weis ,  Till Schloesser ,  Marc Strasser ,  Hannes Luyken

    Inventor： Peng-Fei Wang ,  Joachim Nuetzel ,  Rolf Weis ,  Till Schloesser ,  Marc Strasser ,  Hannes Luyken

    IPC: H01L21/336

    CPC classification number: H01L29/66621 ,  H01L21/28114 ,  H01L27/10876 ,  H01L27/10894 ,  H01L29/42376 ,  H01L29/66545 ,  H01L29/78

    Abstract: A method of manufacturing a transistor is disclosed. The method includes forming a first and a second source/drain regions, a channel connecting the first and the second source/drain regions and a gate electrode for controlling the conductivity of the channel. The gate electrode is formed by defining a gate groove in the substrate, and defining a pocket in each of the isolation trenches at a position adjacent to the groove so that the two pockets will be connected with the groove and the groove is disposed between the two pockets. A gate insulating material is provided at an interface between the active area and the groove and at an interface between the active area and the pockets. A gate electrode material is deposited so as to fill the groove and the two pockets.

    Abstract translation: 公开了制造晶体管的方法。 该方法包括形成第一和第二源极/漏极区域，连接第一和第二源极/漏极区域的沟道和用于控制沟道的导电性的栅电极。 栅极通过在衬底中限定栅极沟槽并且在与沟槽相邻的位置处在每个隔离沟槽中限定一个凹穴形成，使得两个凹穴将与凹槽连接，凹槽设置在两个凹槽之间 口袋 栅极绝缘材料设置在有源区域和凹槽之间的界面处以及在有源区域和凹穴之间的界面处。 沉积栅电极材料以填充凹槽和两个凹穴。

    Lateral semiconductor device and manufacturing method therefor
    4.
    发明授权
    Lateral semiconductor device and manufacturing method therefor 有权
    侧面半导体器件及其制造方法

    公开(公告)号：US08686505B2

    公开(公告)日：2014-04-01

    申请号：US13560109

    申请日：2012-07-27

    Applicant: Marc Strasser ,  Karl-Heinz Gebhardt ,  Ralf Rudolf ,  Lincoln O'Riain

    Inventor： Marc Strasser ,  Karl-Heinz Gebhardt ,  Ralf Rudolf ,  Lincoln O'Riain

    IPC: H01L29/06 ,  H01L29/78 ,  H01L21/301 ,  H01L21/335

    CPC classification number: H01L29/7816 ,  H01L29/063 ,  H01L29/0653 ,  H01L29/0878 ,  H01L29/1095 ,  H01L29/66681

    Abstract: A method produces a semiconductor device including a semiconductor body, an electrode thereon, and an insulating structure insulating the electrode from the semiconductor body. The semiconductor body includes a first contact region of a first conductivity type, a body region of a second conductivity type, a drift region of the first conductivity type, and a second contact region having a higher maximum doping concentration than the drift region. The insulating structure includes a gate dielectric portion forming a first horizontal interface. with the drift region and has a first maximum vertical extension A field dielectric portion forms with the drift region second and third horizontal interfaces arranged below the main surface. A second maximum vertical extension of the field dielectric portion is larger than the first maximum vertical extension. A third maximum vertical extension of the field dielectric portion is larger than the second maximum vertical extension.

    Abstract translation: 一种方法产生半导体器件，其包括半导体本体，其上的电极以及将电极与半导体本体绝缘的绝缘结构。 半导体本体包括第一导电类型的第一接触区域，第二导电类型的体区域，第一导电类型的漂移区域和具有比漂移区域更高的最大掺杂浓度的第二接触区域。 绝缘结构包括形成第一水平界面的栅介质部分。 具有漂移区域并且具有第一最大垂直延伸部A场介电部分形成，漂移区域布置在主表面下方的第二和第三水平界面。 场介电部分的第二最大垂直延伸大于第一最大垂直延伸。 场电介质部分的第三最大垂直延伸大于第二最大垂直延伸。

    Method for producing a trench transistor and trench transistor
    6.
    发明申请
    Method for producing a trench transistor and trench transistor 失效
    沟槽晶体管和沟槽晶体管的制造方法

    公开(公告)号：US20070075361A1

    公开(公告)日：2007-04-05

    申请号：US11529446

    申请日：2006-09-28

    Applicant: Richard Luyken ,  Hans-Peter Moll ,  Martin Popp ,  Till Schloesser ,  Marc Strasser ,  Rolf Weis

    Inventor： Richard Luyken ,  Hans-Peter Moll ,  Martin Popp ,  Till Schloesser ,  Marc Strasser ,  Rolf Weis

    IPC: H01L21/336 ,  H01L29/76

    CPC classification number: H01L21/26586 ,  H01L29/66537 ,  H01L29/66621 ,  H01L29/7834

    Abstract: In a method for producing a trench transistor, a substrate of a first conduction type is provided and a trench in the substrate and a gate dielectric in the trench are formed. A first conductive filling in the trench as a gate electrode on the gate dielectric and first source and drain regions are formed. An etched-back first conductive filling is produced by etching back the first conductive filling down to a depth below the first source and drain regions and second source and drain regions are formed. The second source and drain regions adjoin the first source and drain regions and extend to a depth at least as far as the etched-back first conductive filling. An insulation spacer above the etched-back first conductive filling is formed in the trench and a second conductive filling is provided in the trench as an upper part of the gate electrode.

    Abstract translation: 在制造沟槽晶体管的方法中，提供第一导电类型的衬底，并且形成衬底中的沟槽和沟槽中的栅极电介质。 形成沟槽中作为栅极电介质和第一源极和漏极区域上的栅电极的第一导电填充物。 蚀刻后的第一导电填充物是通过将第一导电填料向下蚀刻回到低于第一源的深度并形成漏极区和第二源极和漏极区而产生的。 第二源极和漏极区域与第一源极和漏极区域相邻并且延伸至至少与蚀刻后的第一导电填充物一样深的深度。 在所述沟槽中形成有在所述蚀刻后的第一导电填充物上方的绝缘间隔物，并且在所述沟槽中设置第二导电填充物作为所述栅电极的上部。

    Memory cell and integrated memory circuit
    7.
    发明申请
    Memory cell and integrated memory circuit 审中-公开
    存储单元和集成存储器电路

    公开(公告)号：US20060118851A1

    公开(公告)日：2006-06-08

    申请号：US11240422

    申请日：2005-09-30

    Applicant: Marc Strasser ,  Bjoern Fischer ,  Ralph Stoemmer

    Inventor： Marc Strasser ,  Bjoern Fischer ,  Ralph Stoemmer

    IPC: H01L29/94

    CPC classification number: H01L29/66181 ,  H01L27/10861

    Abstract: A memory cell is provided for storing a bit. The memory cell includes a capacitor with capacitor electrodes for storing electric charge and a semiconductor switch with a channel region, the electrical conductivity of which is controllable, for connecting the capacitor to a bit line, via which a bit can be written to and read from the memory cell. The channel region and a metallic terminal region connected to one of the capacitor electrodes form a metal-semiconductor junction.

    Abstract translation: 提供存储单元以存储位。 存储单元包括具有用于存储电荷的电容器电极的电容器和具有可控电导率的沟道区域的半导体开关，用于将电容器连接到位线，通过该位线可以将位写入和读取 存储单元。 沟道区域和连接到电容器电极之一的金属端子区形成金属 - 半导体结。

    Lateral Semiconductor Device and Manufacturing Method Therefor
    9.
    发明申请
    Lateral Semiconductor Device and Manufacturing Method Therefor 有权
    侧向半导体器件及其制造方法

    公开(公告)号：US20140027848A1

    公开(公告)日：2014-01-30

    申请号：US13560109

    申请日：2012-07-27

    Applicant: Marc Strasser ,  Karl-Heinz Gebhardt ,  Ralf Rudolf ,  Lincoln O'Riain

    Inventor： Marc Strasser ,  Karl-Heinz Gebhardt ,  Ralf Rudolf ,  Lincoln O'Riain

    IPC: H01L29/78 ,  H01L29/66

    CPC classification number: H01L29/7816 ,  H01L29/063 ,  H01L29/0653 ,  H01L29/0878 ,  H01L29/1095 ,  H01L29/66681

    Abstract: A method produces a semiconductor device including a semiconductor body, an electrode thereon, and an insulating structure insulating the electrode from the semiconductor body. The semiconductor body includes a first contact region of a first conductivity type, a body region of a second conductivity type, a drift region of the first conductivity type, and a second contact region having a higher maximum doping concentration than the drift region. The insulating structure includes a gate dielectric portion forming a first horizontal interface. with the drift region and has a first maximum vertical extension A field dielectric portion forms with the drift region second and third horizontal interfaces arranged below the main surface. A second maximum vertical extension of the field dielectric portion is larger than the first maximum vertical extension. A third maximum vertical extension of the field dielectric portion is larger than the second maximum vertical extension.

    Abstract translation: 一种方法产生半导体器件，其包括半导体本体，其上的电极以及将电极与半导体本体绝缘的绝缘结构。 半导体本体包括第一导电类型的第一接触区域，第二导电类型的体区域，第一导电类型的漂移区域和具有比漂移区域更高的最大掺杂浓度的第二接触区域。 绝缘结构包括形成第一水平界面的栅介质部分。 具有漂移区域并且具有第一最大垂直延伸部A场介电部分形成，漂移区域布置在主表面下方的第二和第三水平界面。 场介电部分的第二最大垂直延伸大于第一最大垂直延伸。 场电介质部分的第三最大垂直延伸大于第二最大垂直延伸。

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