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    Semiconductor memory device having single-level cells and multi-level cells and method of driving the semiconductor memory device
    42.
    发明授权
    Semiconductor memory device having single-level cells and multi-level cells and method of driving the semiconductor memory device 失效
    具有单级单元和多电平单元的半导体存储器件以及驱动半导体存储器件的方法

    公开(公告)号：US07698615B2

    公开(公告)日：2010-04-13

    申请号：US11891991

    申请日：2007-08-14

    Applicant: Eun-suk Kang ,  Young-joon Choi ,  Sang-kil Lee ,  Dae-hyun Lee

    Inventor： Eun-suk Kang ,  Young-joon Choi ,  Sang-kil Lee ,  Dae-hyun Lee

    IPC: H03M13/00

    CPC classification number: G11C11/5621 ,  G11C11/5628 ,  G11C16/0483 ,  G11C29/00 ,  G11C2029/0409 ,  G11C2211/5641

    Abstract: A semiconductor memory device that performs an error control operation when an error exists in an externally received command or an externally received address, and a method of driving the semiconductor memory device are provided. The semiconductor memory device includes a memory cell array having a single-level cell area and a multi-level cell area, a command decoder which receives a command from an external source and decoding the command, an area determination unit which receives an address from an external source and determines whether a memory cell corresponding to the address belongs to either the single-level cell area or the multi-level cell area, a command flag generation unit which generates at least one enable control signal according to the decoded command and the determination result, and a logic circuit which generates a control signal for driving the memory cells included in the memory cell array or performs an error control operation, in response to the enable control signal.

    Abstract translation: 提供了当外部接收的命令或外部接收的地址存在错误时执行错误控制操作的半导体存储器件，以及驱动半导体存储器件的方法。 半导体存储器件包括具有单级单元区域和多级单元区域的存储单元阵列，从外部源接收命令并解码该命令的命令解码器，从 外部源，并且确定与该地址相对应的存储单元是否属于单级单元区域或多级单元区域，命令标志生成单元，其根据解码命令和确定生成至少一个使能控制信号 结果以及响应于使能控制信号产生用于驱动包括在存储单元阵列中的存储单元的控制信号或执行错误控制操作的逻辑电路。

    Method and apparatus for numerically analyzing grain growth on semiconductor wafer using SEM image
    45.
    发明授权
    Method and apparatus for numerically analyzing grain growth on semiconductor wafer using SEM image 失效
    使用SEM图像对半导体晶片上的晶粒生长进行数值分析的方法和装置

    公开(公告)号：US06870948B2

    公开(公告)日：2005-03-22

    申请号：US09977238

    申请日：2001-10-16

    Applicant: Chung-sam Jun ,  Sang-Mun Chon ,  Sang-Bong Choi ,  Kye-Weon Kim ,  Sang-Hoon Lee ,  Yu-Sin Yang ,  Sang-Min Kim ,  Sang-Kil Lee

    Inventor： Chung-sam Jun ,  Sang-Mun Chon ,  Sang-Bong Choi ,  Kye-Weon Kim ,  Sang-Hoon Lee ,  Yu-Sin Yang ,  Sang-Min Kim ,  Sang-Kil Lee

    IPC: G01B15/00 ,  G01B15/08 ,  G01N15/00 ,  G01N15/14 ,  G01N23/20 ,  G01N23/225 ,  G06T1/00 ,  G06T7/00 ,  H01L21/66 ,  G06K9/00 ,  H01L21/8242

    CPC classification number: G06T7/0004 ,  G01N15/1475 ,  G01N2015/0092 ,  G06T2207/30148 ,  H01J2237/2815

    Abstract: A method and apparatus for numerically analyzing a growth degree of grains grown on a surface of a semiconductor wafer, in which the growth degree of grains is automatically calculated and numerated through a computer by using an image file of the surface of the semiconductor wafer scanned by an SEM. A predetermined portion of a surface of the wafer is scanned using the SEM, and the scanned SEM image is simultaneously stored into a database. An automatic numerical program applies meshes to an analysis screen frame and selects an analysis area on a measured image. Thereafter, a smoothing process for reducing an influence of noise is performed on respective pixels designated by the meshes using an average value of image data of adjacent pixels. A standardization process is then performed, based on respective images in order to remove a brightness difference between the measured images. After comparing standardized image data values of the respective pixels with a predetermined threshold value, the number of pixels whose standardized image data value is greater than the threshold value is counted. The growth degree of grains on the surface of the wafer is calculated by numerating a ratio of the counted number with respect to a total number of the pixels contained within the analysis target image.

    Abstract translation: 一种用于数值分析生长在半导体晶片的表面上的晶粒的生长度的方法和装置，其中通过使用由半导体晶片的表面扫描的半导体晶片的表面的图像文件自动计算和计算晶粒的生长度 SEM。 使用SEM扫描晶片的表面的预定部分，并将扫描的SEM图像同时存储到数据库中。 自动数值程序将网格应用于分析屏幕框架，并在测量图像上选择分析区域。 此后，使用相邻像素的图像数据的平均值对由网格指定的各个像素执行用于减少噪声的影响的平滑处理。 然后基于相应的图像执行标准化处理，以便去除所测量的图像之间的亮度差异。 在将各像素的标准化图像数据值与预定阈值进行比较之后，对标准化图像数据值大于阈值的像素数进行计数。 通过对计数的数量相对于分析对象图像中包含的像素的总数的比率进行计算来计算晶片表面上的晶粒的生长度。

    Methods of manufacturing and testing integrated circuit field effect transistors using scanning electron microscope to detect undesired conductive material
    46.
    发明授权
    Methods of manufacturing and testing integrated circuit field effect transistors using scanning electron microscope to detect undesired conductive material 失效
    使用扫描电子显微镜制造和测试集成电路场效应晶体管的方法来检测不期望的导电材料

    公开(公告)号：US6150185A

    公开(公告)日：2000-11-21

    申请号：US67195

    申请日：1998-04-27

    Applicant: Sang-hun Lee ,  Yong-ju Kim ,  Sang-kyu Hahm ,  Sang-kil Lee

    Inventor： Sang-hun Lee ,  Yong-ju Kim ,  Sang-kyu Hahm ,  Sang-kil Lee

    IPC: H01L21/28 ,  H01L21/336 ,  H01L21/66 ,  H01L29/78 ,  H01L21/00

    CPC classification number: B24B37/013 ,  H01L22/26 ,  H01L22/12

    Abstract: Scanning Electron Microscope (SEM) analysis is used to detect undesired conductive material on the gate sidewall spacers. The undesired conductive material is then etched from the sidewall spacers if the undesired material is detected by the SEM analysis. More specifically, integrated circuit field effect transistors may be manufactured by forming on an integrated circuit substrate, a plurality of field effect transistors, each comprising spaced apart source and drain regions, a gate therebetween including a sidewall, a sidewall spacer on the sidewall and contacts comprising conductive material on the source and drain regions. At least one of the field effect transistors may include undesired conductive material on the sidewall spacer thereof. The integrated circuit field effect transistors are tested by performing SEM analysis on the integrated circuit substrate to detect the undesired conductive material on the sidewall spacer. The undesired conductive material is then etched from the sidewall spacer if the undesired material is detected by the SEM analysis.

    Abstract translation: 扫描电子显微镜（SEM）分析用于检测栅极侧壁间隔物上的不期望的导电材料。 如果通过SEM分析检测到不需要的材料，则从侧壁间隔物蚀刻不需要的导电材料。 更具体地，可以通过在集成电路基板上形成多个场效应晶体管来制造集成电路场效应晶体管，多个场效应晶体管每个包括间隔开的源极和漏极区，其间的栅极包括侧壁，侧壁上的侧壁间隔物和接触 在源极和漏极区域上包括导电材料。 至少一个场效应晶体管可以在其侧壁间隔物上包括不期望的导电材料。 通过在集成电路基板上进行SEM分析来测试集成电路场效应晶体管，以检测侧壁间隔物上的不期望的导电材料。 如果通过SEM分析检测到不需要的材料，则从侧壁间隔物中蚀刻出不期望的导电材料。

    BROADBAND LIGHT SOURCE AND OPTICAL INSPECTOR HAVING THE SAME
    47.
    发明申请
    BROADBAND LIGHT SOURCE AND OPTICAL INSPECTOR HAVING THE SAME 有权
    宽光源光源和具有该光源的光学检测器

    公开(公告)号：US20160097513A1

    公开(公告)日：2016-04-07

    申请号：US14872228

    申请日：2015-10-01

    Applicant: Sung-Yoon RYU ,  Woo-Seok KO ,  Yu-Sin YANG ,  Sang-Kil LEE ,  Chung-Sam JUN ,  Seong-Jin YUN

    Inventor： Sung-Yoon RYU ,  Woo-Seok KO ,  Yu-Sin YANG ,  Sang-Kil LEE ,  Chung-Sam JUN ,  Seong-Jin YUN

    IPC: F21V7/04 ,  H01S3/00 ,  F21V7/08

    CPC classification number: H01S3/0071 ,  G01N21/8806 ,  G01N21/956

    Abstract: A broadband light source includes a first electrodeless lamp to generate first broadband light from plasma, a first elliptical reflector having first and second focuses, the first elliptical reflector enclosing a rear portion of the first electrodeless lamp positioned at the first focus of the first elliptical reflector such that the first broadband light is reflected from the first elliptical reflector toward a light collector as a collective light, a symmetrically curved reflector having a third focus, the symmetrically curved reflector positioned such that the third focus is coincident with one of the first and second focuses, and a laser irradiator to provide a laser beam to the first electrodeless lamp.

    Abstract translation: 宽带光源包括第一无电极灯以产生来自等离子体的第一宽带光，具有第一和第二焦点的第一椭圆形反射器，第一椭圆形反射器包围位于第一椭圆形反射器的第一焦点处的第一无电极灯的后部 使得第一宽带光从第一椭圆形反射器朝向聚光器反射，作为集体光，具有第三焦点的对称弯曲反射器，对称弯曲的反射器被定位成使得第三焦点与第一和第二光焦度中的一个重合 焦点和激光照射器，以向第一无电极灯提供激光束。

    OVERLAY MEASURING METHOD AND SYSTEM, AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE USING THE SAME
    48.
    发明申请
    OVERLAY MEASURING METHOD AND SYSTEM, AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE USING THE SAME 有权
    重叠测量方法和系统以及使用其制造半导体器件的方法

    公开(公告)号：US20160013109A1

    公开(公告)日：2016-01-14

    申请号：US14796478

    申请日：2015-07-10

    Applicant: Seong-Jin YUN ,  Woo-Seok KO ,  Yu-Sin YANG ,  Sang-Kil LEE ,  Chung-Sam JUN

    Inventor： Seong-Jin YUN ,  Woo-Seok KO ,  Yu-Sin YANG ,  Sang-Kil LEE ,  Chung-Sam JUN

    IPC: H01L21/66 ,  H01J37/26

    CPC classification number: H01L22/20 ,  H01J37/222 ,  H01J2237/221 ,  H01J2237/2617 ,  H01J2237/2817

    Abstract: An overlay measuring method includes irradiating an electron beam onto a sample, including a multi-layered structure of overlapped upper and lower patterns formed thereon, to obtain an actual image of the upper and lower patterns. A first image representing the upper pattern and a second image representing the lower pattern are obtained from the actual image. A reference position for the upper and lower patterns is determined from a design image of the upper and lower patterns. A position deviation of the upper pattern with respect to the reference position in the first image and a position deviation of the lower pattern with respect to the reference position in the second image are calculated to determine an overlay between the upper pattern and the lower pattern.

    Abstract translation: 覆盖测量方法包括将电子束照射到样品上，包括形成在其上的重叠的上下图案的多层结构，以获得上下图案的实际图像。 从实际图像中获得代表上部图案的第一图像和表示较低图案的第二图像。 根据上下图案的设计图像确定上下图案的参考位置。 计算上部图形相对于第一图像中的基准位置的位置偏差和下部图形相对于第二图像中的基准位置的位置偏差，以确定上部图案和下部图案之间的叠加。

    Microelectronic substrate inspection equipment using helium ion microscopy
    49.
    发明授权
    Microelectronic substrate inspection equipment using helium ion microscopy 有权
    微电子基板检测设备采用氦离子显微镜

    公开(公告)号：US08729468B2

    公开(公告)日：2014-05-20

    申请号：US13596644

    申请日：2012-08-28

    Applicant: Min-Kook Kim ,  Woo-Seok Ko ,  Yu-Sin Yang ,  Sang-Kil Lee ,  Chang-Hoon Choi

    Inventor： Min-Kook Kim ,  Woo-Seok Ko ,  Yu-Sin Yang ,  Sang-Kil Lee ,  Chang-Hoon Choi

    IPC: H01J37/26

    CPC classification number: H01J37/265 ,  H01J37/08 ,  H01J2237/002 ,  H01J2237/006 ,  H01J2237/0807

    Abstract: Microelectronic substrate inspection equipment includes a gas container which contains helium gas, a helium ion generator which is disposed in the gas container and converts the helium gas into helium ions and a wafer stage which is disposed under the gas container and on which a substrate to be inspected is placed. The equipment further includes a secondary electron detector which is disposed above the wafer stage and detects electrons generated from the substrate, a compressor which receives first gaseous nitrogen from a continuous nitrogen supply device and compresses the received first gaseous nitrogen into liquid nitrogen, a liquid nitrogen dewar which is connected to the compressor and stores the liquid nitrogen, and a cooling device that is coupled to the helium ion generator. The cooling device is disposed on the gas container, and cools the helium ion generator by vaporizing the liquid nitrogen. Related methods are also disclosed.

    Abstract translation: 微电子基板检查设备包括含有氦气的气体容器，设置在气体容器中并将氦气转换为氦离子的氦离子发生器和设置在气体容器下方的晶片载台， 检查被放置。 该设备还包括二次电子检测器，其设置在晶片台上方并检测从基板产生的电子;压缩机，其接收来自连续氮供应装置的第一气态氮并将接收到的第一气态氮压缩成液态氮;液氮 连接到压缩机并储存液氮的杜瓦瓶，以及耦合到氦离子发生器的冷却装置。 冷却装置设置在气体容器上，并通过蒸发液氮来冷却氦离子发生器。 还公开了相关方法。

    DEFECT INSPECTION APPARATUS AND DEFECT INSPECTION METHOD USING THE SAME
    50.
    发明申请
    DEFECT INSPECTION APPARATUS AND DEFECT INSPECTION METHOD USING THE SAME 有权
    缺陷检查装置和缺陷检查方法

    公开(公告)号：US20120314205A1

    公开(公告)日：2012-12-13

    申请号：US13472145

    申请日：2012-05-15

    Applicant: Young-Hoon SOHN ,  Yu-Sin YANG ,  Sang-Kil LEE

    Inventor： Young-Hoon SOHN ,  Yu-Sin YANG ,  Sang-Kil LEE

    IPC: G01N21/88 ,  G01R31/00

    CPC classification number: G01N21/55 ,  G01N21/9501

    Abstract: A defect inspection apparatus comprises a table on which a substrate is placed, a first detection unit which is disposed above the table to detect an optical signal from the substrate, a second detection unit which is disposed above the table to detect an electrical signal from the substrate, and a signal processing unit which is connected to the first detection unit and the second detection unit to detect a chemical defect using the optical signal and the electrical signal.

    Abstract translation: 缺陷检查装置包括：放置基板的工作台，设置在工作台上方以检测来自衬底的光信号的第一检测单元，设置在工作台上方的第二检测单元，用于检测来自基板的电信号; 基板和连接到第一检测单元和第二检测单元的信号处理单元，以使用光信号和电信号来检测化学缺陷。

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