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    Incremental register retiming of an integrated circuit design
    43.
    发明授权
    Incremental register retiming of an integrated circuit design 有权

    公开(公告)号：US10387603B2

    公开(公告)日：2019-08-20

    申请号：US16002988

    申请日：2018-06-07

    Applicant: Altera Corporation

    Inventor： Nishanth Sinnadurai ,  Gordon Raymond Chiu

    IPC: G06F17/50

    Abstract: A first circuit design description may have registers and combinational gates. Circuit design computing equipment may perform register retiming on the first circuit design description, whereby registers are moved across combinational gates during a first circuit design implementation. An engineering-change-order (ECO) of the first circuit design may result in a second circuit design. The differences between the first and second circuit designs may be confined to a region-of-change. The circuit design computing equipment may preserve the results from the first circuit design implementation and re-use portions of these results during the implementation of the second circuit design. For example, the circuit design computing equipment may preserve the register retiming solution from the first circuit design implementation for portions of the second circuit design that are outside the region-of-change and incrementally create graphs that allow to incrementally solve the register retiming problem during the second circuit design implementation.

    INCREMENTAL REGISTER RETIMING OF AN INTEGRATED CIRCUIT DESIGN
    44.
    发明申请
    INCREMENTAL REGISTER RETIMING OF AN INTEGRATED CIRCUIT DESIGN 审中-公开

    公开(公告)号：US20180293343A1

    公开(公告)日：2018-10-11

    申请号：US16002988

    申请日：2018-06-07

    Applicant: Altera Corporation

    Inventor： Nishanth Sinnadurai ,  Gordon Raymond Chiu

    IPC: G06F17/50

    CPC classification number: G06F17/5072 ,  G06F17/5054 ,  G06F17/5081 ,  G06F2217/84

    Abstract: A first circuit design description may have registers and combinational gates. Circuit design computing equipment may perform register retiming on the first circuit design description, whereby registers are moved across combinational gates during a first circuit design implementation. An engineering-change-order (ECO) of the first circuit design may result in a second circuit design. The differences between the first and second circuit designs may be confined to a region-of-change. The circuit design computing equipment may preserve the results from the first circuit design implementation and re-use portions of these results during the implementation of the second circuit design. For example, the circuit design computing equipment may preserve the register retiming solution from the first circuit design implementation for portions of the second circuit design that are outside the region-of-change and incrementally create graphs that allow to incrementally solve the register retiming problem during the second circuit design implementation.

    CIRCUITS AND METHODS FOR DQS AUTOGATING
    46.
    发明申请
    CIRCUITS AND METHODS FOR DQS AUTOGATING 审中-公开

    公开(公告)号：US20170270995A1

    公开(公告)日：2017-09-21

    申请号：US15614221

    申请日：2017-06-05

    Applicant: Altera Corporation

    Inventor： Krzysztof Maryan ,  Gordon Raymond Chiu ,  Warren Nordyke ,  Navid Azizi

    IPC: G11C11/4076 ,  G06F1/12 ,  G11C11/4093 ,  G11C7/10 ,  G11C8/18 ,  G11C29/02

    CPC classification number: G11C11/4076 ,  G06F1/12 ,  G11C7/1087 ,  G11C7/1093 ,  G11C8/18 ,  G11C11/4093 ,  G11C29/023

    Abstract: In one aspect, a method includes receiving a differential strobe signal including first and second components; buffering, by a first buffer, both the first and second components; and buffering, by a second buffer, the first component. The method includes receiving, by a control logic block, the output of the second buffer. The method includes, after a period when the values of both the first and second components are at a first logic state, but before receiving a burst of clock edges in the differential strobe signal, detecting a transition in the first component from the first logic state to a second logic state, and in response to the detected transition, asserting an enable signal. The method further includes receiving, by a gating logic block, the enable signal and the output of the first buffer, and, when the enable signal is asserted, un-gating the output of the first buffer.

    INCREMENTAL REGISTER RETIMING OF AN INTEGRATED CIRCUIT DESIGN
    48.
    发明申请
    INCREMENTAL REGISTER RETIMING OF AN INTEGRATED CIRCUIT DESIGN 有权
    集成电路设计的增量寄存器退化

    公开(公告)号：US20170068765A1

    公开(公告)日：2017-03-09

    申请号：US14846645

    申请日：2015-09-04

    Applicant: Altera Corporation

    Inventor： Nishanth Sinnadurai ,  Gordon Raymond Chiu

    IPC: G06F17/50

    CPC classification number: G06F17/5072 ,  G06F17/5054 ,  G06F17/5081 ,  G06F2217/84

    Abstract: A first circuit design description may have registers and combinational gates. Circuit design computing equipment may perform register retiming on the first circuit design description, whereby registers are moved across combinational gates during a first circuit design implementation. An engineering-change-order (ECO) of the first circuit design may result in a second circuit design. The differences between the first and second circuit designs may be confined to a region-of-change. The circuit design computing equipment may preserve the results from the first circuit design implementation and re-use portions of these results during the implementation of the second circuit design. For example, the circuit design computing equipment may preserve the register retiming solution from the first circuit design implementation for portions of the second circuit design that are outside the region-of-change and incrementally create graphs that allow to incrementally solve the register retiming problem during the second circuit design implementation.

    Abstract translation: 第一电路设计描述可以具有寄存器和组合门。 电路设计计算设备可以在第一电路设计描述上执行寄存器重新定时，由此在第一电路设计实现期间寄存器移动到组合门上。 第一电路设计的工程改变顺序（ECO）可能导致第二电路设计。 第一和第二电路设计之间的差异可以局限于变化的区域。 电路设计计算设备可以保留来自第一电路设计实现的结果，并且在实施第二电路设计期间重新使用这些结果的部分。 例如，电路设计计算设备可以保留来自第一电路设计实现的寄存器重新定时解决方案，用于在变化范围之外的第二电路设计的部分，并且增量地创建允许递增地解决寄存器重定时问题的图形 第二电路设计实现。

    METHODS FOR PERFORMING REGISTER RETIMING OPERATIONS INTO SYNCHRONIZATION REGIONS INTERPOSED BETWEEN CIRCUITS ASSOCIATED WITH DIFFERENT CLOCK DOMAINS
    49.
    发明申请
    METHODS FOR PERFORMING REGISTER RETIMING OPERATIONS INTO SYNCHRONIZATION REGIONS INTERPOSED BETWEEN CIRCUITS ASSOCIATED WITH DIFFERENT CLOCK DOMAINS 审中-公开
    将注册表返回操作进入与不同时钟域相关联的电路之间的同步区域的方法

    公开(公告)号：US20160357899A1

    公开(公告)日：2016-12-08

    申请号：US14730082

    申请日：2015-06-03

    Applicant: Altera Corporation

    Inventor： Benjamin Gamsa ,  Gordon Raymond Chiu

    IPC: G06F17/50

    CPC classification number: G06F17/5054 ,  G06F17/505 ,  G06F2217/84

    Abstract: Circuit design computing equipment may perform register retiming operations to improve the performance of a circuit design after having performed placement and routing operations. For example, the circuit design computing equipment may perform register retiming operations that move registers from a first portion of a circuit design that operates in a first clock domain into a synchronization region that separates the first portion of the circuit design from a second portion of the circuit design that operates in a second clock domain that is different than the first clock domain. Performing register retiming operations that move registers into a synchronization region between clock domains may solve the so-called short path—long path problem in which a long path that would benefit from a register retiming operation is coupled in parallel to a short path that has no location to receive a register during the register retiming operation.

    Abstract translation: 电路设计计算设备可以执行寄存器重新定时操作，以在执行放置和布线操作之后改善电路设计的性能。 例如，电路设计计算设备可以执行寄存器重定时操作，其将寄存器从在第一时钟域中操作的电路设计的第一部分移动到将电路设计的第一部分与电路设计的第二部分分开的同步区域 电路设计在与第一时钟域不同的第二时钟域中工作。 将寄存器迁移到时钟域之间的同步区域的执行寄存器重新定时操作可以解决所谓的短路径长路径问题，其中将从寄存器重定时操作中受益的长路径并行耦合到没有 在寄存器重新定时操作期间接收寄存器的位置。

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